公开(公告)号：US20160148691A1

公开(公告)日：2016-05-26

申请号：US14550897

申请日：2014-11-21

Applicant: SanDisk Technologies Inc.

Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

IPC: G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

Abstract translation: 描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。 存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。 在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。 在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时 存储器阵列和存储器阵列内的未选择字线组的位置。

公开(公告)号：US20160147671A1

公开(公告)日：2016-05-26

申请号：US14551980

申请日：2014-11-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： GADI VISHNE ,  ERAN EREZ ,  ROMAN ROZENTAL ,  POLINA MARIMONT ,  JUDAH GAMLIEL HAHN

IPC: G06F12/12

CPC classification number: G06F12/12 ,  G06F12/0246 ,  G06F12/0844 ,  G06F12/0868 ,  G06F2212/1041

Abstract: A data storage device includes a write cache, a non-volatile memory, and a controller coupled to the write cache and to the non-volatile memory. The controller is configured to, responsive to receiving a command to flush particular data from the write cache, attempt to fill a write block of data using the particular data and pending data obtained after receipt of the command.

Abstract translation: 数据存储设备包括写高速缓存，非易失性存储器和耦合到写高速缓存和非易失性存储器的控制器。 控制器被配置为响应于接收到从写入高速缓冲存储特定数据的命令，尝试使用特定数据和在接收到命令之后获得的待处理数据来填充数据的写入块。

公开(公告)号：USRE46014E1

公开(公告)日：2016-05-24

申请号：US14285459

申请日：2014-05-22

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： Manabu Sakai ,  Toru Miwa

IPC: G11C16/04 ,  G11C29/02 ,  G11C11/56 ,  G11C29/12

CPC classification number: G11C29/025 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2029/1202 ,  G11C2211/5621

Abstract: Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.

Abstract translation: 提供了用于检测字线中的缺陷的方法和非易失性存储系统。 可能检测到“破碎”的字线缺陷。 可以保持关于哪些存储元件被编程为跟踪状态的信息。 然后，在完成编程之后，读取存储元件以确定哪些存储元件具有低于与跟踪状态相关联的参考电压电平的阈值电压。 通过跟踪哪些存储元件处于跟踪状态，可以滤除与其他状态相关联的元件，使得可以对哪些存储元件被编程不正确进行准确的评估。 根据该信息，可以确定字线是否有缺陷。 例如，如果存储元素太多被编程不当，则这可能表示一个破损的字线。

公开(公告)号：US09349458B2

公开(公告)日：2016-05-24

申请号：US14515762

申请日：2014-10-16

Applicant: SanDisk Technologies, Inc.

Inventor： Kenneth Se Mon Louie ,  Khanh Nguyen

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115

CPC classification number: G11C16/08 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/16 ,  G11C2213/71 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

Abstract: Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.

Abstract translation: 提出了用于减少用于解码多块组中的存储器块的NAND型存储器的源极线上的负载的技术，BiCS类型的示例3D NAND存储器。 当多个块被共同解码时，解码组可以包括选择块和未选择的块。 所选块的字线根据操作偏置，而组的未选择块的字线被设置在源极线的电平。 这由于源极线和字线之间的较小电容而减少了源极线上的负载量。

公开(公告)号：US09342446B2

公开(公告)日：2016-05-17

申请号：US13074402

申请日：2011-03-29

Applicant: Neil David Hutchison ,  Robert George Young

Inventor： Neil David Hutchison ,  Robert George Young

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203

Abstract: A non-volatile memory system includes a memory section having a non-volatile cache portion storing data in a binary format, a primary user data storage section that stores user data in multi-state format, and an update memory area where the memory system stores data updating user data previously stored in the primary user data. The memory system allows a maximum number of blocks for use in the update memory area. When the memory system receives updated data corresponding to user data already written into the primary user data storage section, it determines whether a block of memory is available in the update memory area. In response to determining that a block of memory is not available in the update memory area, the system determines a block of the update memory to remove from the update memory; copies the data content of the determined update block into the cache portion of the memory section; and subsequently writes the updated data into the update memory.

Abstract translation: 非易失性存储器系统包括具有以二进制格式存储数据的非易失性高速缓存部分的存储器部分，以多状态格式存储用户数据的主用户数据存储部分和存储器系统存储的更新存储器区域 数据更新先前存储在主用户数据中的用户数据。 存储器系统允许在更新存储器区域中使用最大数量的块。 当存储器系统接收与已经写入主用户数据存储部分的用户数据相对应的更新数据时，它确定更新存储器区域中存储器块是否可用。 响应于确定存储器块在更新存储器区域中不可用，系统确定要从更新存储器中移除的更新存储器的块; 将确定的更新块的数据内容复制到存储器部分的高速缓存部分中; 并随后将更新的数据写入更新存储器。

公开(公告)号：US20160133324A1

公开(公告)日：2016-05-12

申请号：US14539033

申请日：2014-11-12

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： IDAN ALROD ,  NOAM PRESMAN ,  ARIEL NAVON ,  TZ-YI LIU ,  TIANHONG YAN

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C7/1006 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2213/77

Abstract: A method includes, in a data storage device including a resistive memory, receiving an erase command to erase a portion of the resistive memory. The method further includes sending shaped data to be stored at the portion of the resistive memory responsive to the erase command.

Abstract translation: 一种方法包括在包括电阻性存储器的数据存储装置中，接收擦除指令以擦除电阻性存储器的一部分。 该方法还包括响应于擦除命令发送要存储在电阻存储器部分的成形数据。

公开(公告)号：US09336892B1

公开(公告)日：2016-05-10

申请号：US14728615

申请日：2015-06-02

Applicant: SanDisk Technologies Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong ,  Charles Kwong

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5621

Abstract: Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, the magnitude of a selected word line voltage is increased to be equal to pass voltages of unselected word lines, and the selected and unselected word line are ramped down at the same time, to avoid creating a channel gradient. In an example verify operation, the above procedure can be followed when the selected word line is at a source-side or middle range among all word lines. When the selected word line is at a drain-side among all word lines, a source-side select gate can be ramped down before the selected word line and a drain-side select gate can be ramped down after the selected word line.

Abstract translation: 通过控制字线的幅度和时序并在感测操作结束时选择栅极斜坡下降电压，在3D存储器件中减少了由于热电子注入引起的读取干扰。 在示例性读取操作中，所选择的字线电压的大小增加到等于未选择字线的通过电压，并且所选择的和未选择的字线同时斜降，以避免产生通道梯度。 在示例验证操作中，当所选字线在所有字线之间的源侧或中间范围时，可以遵循上述过程。 当所选择的字线位于所有字线之间的漏极侧时，在选择的字线之前可以使源极选择栅极向下斜坡，并且在选择的字线之后，可以将漏极侧选择栅极向下斜坡。

公开(公告)号：US09336891B2

公开(公告)日：2016-05-10

申请号：US14322055

申请日：2014-07-02

Applicant: SanDisk Technologies Inc.

Inventor： Jiahui Yuan ,  Yingda Dong ,  Wei Zhao

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  H01L27/115

CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5648 ,  H01L27/1157 ,  H01L27/11582

Abstract: A read operation for selected memory cell on a selected word line compensates for program disturb which is a nonlinear function of the data state of an adjacent memory cell on an adjacent word line. When a command to perform a read operation for the selected memory cell is received, a read operation is first performed on the adjacent memory cell to determine its data state, or to classify the adjacent memory cell into a threshold voltage range which includes one or more data states, or a portion of a data state. The selected memory cell is then read using a baseline control gate voltage which does not provide compensation, and one or more elevated control gate voltages which provide compensation, to distinguish between two adjacent data states. An optimal sensing result is selected based on the data state or threshold voltage range of the adjacent memory cell.

Abstract translation: 对所选择的字线上的所选存储单元的读操作补偿作为相邻字线上相邻存储单元的数据状态的非线性函数的程序干扰。 当接收到对所选择的存储单元执行读取操作的命令时，首先对相邻的存储器单元执行读取操作以确定其数据状态，或将相邻的存储器单元分类为包括一个或多个 数据状态或数据状态的一部分。 然后使用不提供补偿的基线控制栅极电压以及提供补偿的一个或多个升高的​​控制栅极电压来读取所选择的存储器单元，以区分两个相邻的数据状态。 基于相邻存储单元的数据状态或阈值电压范围来选择最佳感测结果。

公开(公告)号：US09336133B2

公开(公告)日：2016-05-10

申请号：US13826738

申请日：2013-03-14

Applicant: SanDisk Technologies Inc.

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F12/02 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C11/56 ,  G11C2211/5641

Abstract: A system and method for managing program cycles in a multi-layer memory are disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request. The programming cycle may be a set of a host data write programming operation and any maintenance programming operations on an amount of data already programmed in the plurality of memory layers that is necessary to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the host request, and the amount of data to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle.

Abstract translation: 公开了一种用于管理多层存储器中的程序循环的系统和方法。 该方法包括控制器，其接收来自主机的数据编程请求，并且在编程与该请求相关联的数据之前，确定用于编程与该请求相关联的数据的程序周期。 编程周期可以是一组主机数据写入编程操作以及对已经在多个存储器层中编程的数据量的任何维护编程操作，这些数据量是必需的，以提供用于后续请求从主机编程数据的空闲存储器容量 。 控制器根据所确定的程序周期，在预定的编程单元中编程与主机请求相关联的数据以及在维护操作中要编程的数据量。

公开(公告)号：US09336130B2

公开(公告)日：2016-05-10

申请号：US13308117

申请日：2011-11-30

Applicant: Mahmud Asfur ,  Yonatan Tzafrir

Inventor： Mahmud Asfur ,  Yonatan Tzafrir

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/02 ,  G06F13/1684

Abstract: Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.

Abstract translation: 用于在相同非易失性存储器上提供BIOS数据和非BIOS数据的方法，系统和计算机可读介质。 根据一个方面，用于在相同的非易失性存储器上提供BIOS数据和非BIOS数据的系统包括：控制器，用于控制主机对用于存储数据的非易失性存储器的访问，所述数据包括BIOS数据和非易失性存储器， BIOS数据。 所述控制器包括用于经由第一总线协议的第一总线向主机传送数据和从主机传送数据的第一总线接口，用于经由第二总线协议的第二总线向主机传送数据和从主机传送数据的第二总线接口，以及第三总线 用于向非易失性存储器传送数据的接口。 第一个总线包括一个总线，该总线在上电复位后和BIOS访问之前可操作。