公开(公告)号：US20240363539A1

公开(公告)日：2024-10-31

申请号：US18764355

申请日：2024-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US12119272B2

公开(公告)日：2024-10-15

申请号：US18233331

申请日：2023-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

公开(公告)号：US11749743B2

公开(公告)日：2023-09-05

申请号：US17968778

申请日：2022-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31116

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US11527448B2

公开(公告)日：2022-12-13

申请号：US17134465

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

公开(公告)号：US20220238632A1

公开(公告)日：2022-07-28

申请号：US17160319

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chi-Mao Hsu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Hsin-Fu Huang

IPC: H01L49/02 ,  H01C7/00 ,  H01C17/08

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

公开(公告)号：US11239243B2

公开(公告)日：2022-02-01

申请号：US16866573

申请日：2020-05-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

公开(公告)号：US20210210617A1

公开(公告)日：2021-07-08

申请号：US17209244

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750° C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

公开(公告)号：US10991810B2

公开(公告)日：2021-04-27

申请号：US17008633

申请日：2020-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate, forming a polymer block on a corner between the gate structure and the substrate, performing an oxidation process to form a first seal layer on sidewalls of the gate structure, and forming a source/drain region adjacent to two sides of the gate structure. Preferably, the polymer block includes fluorine, bromide, or silicon.

公开(公告)号：US20200350317A1

公开(公告)日：2020-11-05

申请号：US16931397

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10756090B2

公开(公告)日：2020-08-25

申请号：US15922899

申请日：2018-03-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L21/8242 ,  H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L21/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).