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公开(公告)号：US12147784B2
公开(公告)日：2024-11-19
申请号：US17387598
申请日：2021-07-28
Inventor： Po-Hao Lee , Chia-Fu Lee , Yi-Chun Shih , Yu-Der Chih , Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao
IPC: G06F7/544 , G11C11/412
Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.
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公开(公告)号：US20240379183A1
公开(公告)日：2024-11-14
申请号：US18314825
申请日：2023-05-10
Inventor： Po-Hao Lee , Chia-Fu Lee , Yu-Der Chih
Abstract: A method for testing and repairing a memory device is provided. The memory device includes a memory array having data cells and reference cells arranged along cell rows and cell columns. The data cells are configured to store data, and the reference cells are configured to generate a reference current for reading the data stored in the data cells. The method includes: performing a row repair, to test the reference cells in each cell row, and to replace the cell row containing at least one defective reference cell by a redundant cell row comprising additional data cells and additional reference cells; and performing a local reference current trimming, to modify a ratio of an amount of the reference cells programmed with a low resistance state over an amount of the reference cells programmed with a high resistance state for at least one of the cell rows.
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公开(公告)号：US20230343391A1
公开(公告)日：2023-10-26
申请号：US18345071
申请日：2023-06-30
Inventor： Po-Hao Lee , Chia-Fu Lee , Yi-Chun Shih
IPC: G11C13/00
CPC classification number: G11C13/0028
Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
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公开(公告)号：US20230315389A1
公开(公告)日：2023-10-05
申请号：US17855089
申请日：2022-06-30
Inventor： Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao , Chia-Fu Lee , Nail Etkin Can AKKAYA , Mahmut Sinangil
IPC: G06F7/57
CPC classification number: G06F7/57 , G11C11/401
Abstract: A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.
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公开(公告)号：US20230223062A1
公开(公告)日：2023-07-13
申请号：US18175087
申请日：2023-02-27
Inventor： Po-Hao Lee , Chia-Fu Lee , Yi-Chun Shih
CPC classification number: G11C11/005 , G11C11/1659 , G11C11/1675 , G11C17/16 , G11C17/18
Abstract: A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.
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Patent Agency Ranking
公开(公告)号：US20220247394A1
公开(公告)日：2022-08-04
申请号：US17162440
申请日：2021-01-29
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: H03K3/356
Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
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公开(公告)号：US11367468B1
公开(公告)日：2022-06-21
申请号：US17186250
申请日：2021-02-26
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
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公开(公告)号：US11250908B2
公开(公告)日：2022-02-15
申请号：US16544309
申请日：2019-08-19
Inventor： Yu-Der Chih , Chia-Fu Lee , Yi-Chun Shih , Hon-Jarn Lin , Ku-Feng Lin
Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.
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公开(公告)号：US11195562B2
公开(公告)日：2021-12-07
申请号：US16870220
申请日：2020-05-08
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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公开(公告)号：US20210358532A1
公开(公告)日：2021-11-18
申请号：US17391639
申请日：2021-08-02
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Po-Hao Lee , Ku-Feng Lin , Yi-Chun Shih , Yu-Der Chih
Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
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