公开(公告)号：US10176147B2

公开(公告)日：2019-01-08

申请号：US15452299

申请日：2017-03-07

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Amin Ansari ,  Yang Du

IPC: G06F9/30 ,  G06F15/80 ,  H01L21/00 ,  H01L25/00 ,  H01L27/00 ,  G06F9/38 ,  G06F12/0875 ,  G06F15/76 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：US10121743B2

公开(公告)日：2018-11-06

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US10062680B2

公开(公告)日：2018-08-28

申请号：US14272981

申请日：2014-05-08

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H03K3/012 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/78696 ,  H03K3/012

Abstract: Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.

公开(公告)号：US09922956B2

公开(公告)日：2018-03-20

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Wenyue Zhang ,  Yang Du ,  Yong Ju Lee ,  Shiqun Gu ,  Jing Xie

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L27/06 ,  H01L21/822

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

公开(公告)号：US09869713B2

公开(公告)日：2018-01-16

申请号：US14639511

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Ratibor Radojcic ,  Yang Du

IPC: G01R31/02 ,  G01R31/28 ,  G01R19/165 ,  H01L23/48 ,  H01L23/58 ,  H01L23/64 ,  H01L27/06 ,  H01L21/66 ,  G01R31/3185

CPC classification number: G01R31/2851 ,  G01R19/16533 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/585 ,  H01L23/647 ,  H01L27/0688

Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

公开(公告)号：US09754923B1

公开(公告)日：2017-09-05

申请号：US15149646

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du ,  Javid Jaffari

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G06F17/50 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L25/16 ,  H01L27/0688 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434

Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

公开(公告)号：US09741691B2

公开(公告)日：2017-08-22

申请号：US14698842

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Yang Du

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L27/06 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05147 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73153 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.

公开(公告)号：US09626311B2

公开(公告)日：2017-04-18

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L23/48 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/4282 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06544

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

公开(公告)号：US09583473B2

公开(公告)日：2017-02-28

申请号：US15231836

申请日：2016-08-09

Applicant: QUALCOMM Incorporated

Inventor： Yang Du

IPC: H04Q5/22 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L21/77 ,  H01L21/8221 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/06544 ,  Y10T29/41 ,  H01L2924/00014

Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.

Abstract translation: 在详细描述中公开的实施例包括使用单片三维（3D）集成电路（IC）（3DIC）（3DIC）集成技术的完整的片上系统（SOC）解决方案。 本公开包括定制单片3DIC内的层的能力的示例以及通过整体式层间通孔（MIV）在层之间可能的伴随的短互连以在芯片上创建系统的示例。 特别地，3DIC的不同层被构造成支持不同的功能并且符合不同的设计标准。 因此，3DIC可以具有模拟层，具有较高电压阈值的层，具有较低漏电流的层，不同材料层，以实现需要不同基底材料等的部件。 与堆叠的模具不同，上层可以与下层具有相同的尺寸，因为不需要外部布线连接。

公开(公告)号：US20160217087A1

公开(公告)日：2016-07-28

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L25/00 ,  H01L23/50 ,  H01L23/48 ,  H01L25/18

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/4282 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06544

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract translation: 在详细描述中公开的方面包括采用分布式硅通孔（TSV）农场的三维（3D）集成电路（IC）（3DIC）中的存储器控​​制器放置。 在这方面，在一方面，存储器控制器基于分布式TSV场内的集中式存储器控制器放置方案而设置在3DIC中。 存储器控制器可以放置在多个TSV农场中的几何中心处，以在存储器控制器和多个TSV农场中的每一个之间提供大致相等的线长度。 在另一方面，基于分布式存储器控制器放置方案在3DIC中提供多个存储器控制器，其中多个存储器控制器中的每一个与多个TSV农场中的相应TSV场相邻放置。 通过在3DIC中基于集中式存储器控制器放置方案和/或分布式存储器控制器放置方案布置存储器控制器，存储器访问请求的等待时间最小化。