公开(公告)号：US20250060776A1

公开(公告)日：2025-02-20

申请号：US18449567

申请日：2023-08-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

IPC: G06F1/08

Abstract: A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

公开(公告)号：US20240323691A1

公开(公告)日：2024-09-26

申请号：US18188652

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic WIETFELDT ,  Philip Michael HAWKES ,  William WHYTE ,  Jonathan PETIT

IPC: H04W12/106 ,  H04W4/38

CPC classification number: H04W12/106 ,  H04W4/38

Abstract: A processing circuit is coupled to imaging devices through multiple data communication links. Each data communication link couples at least one imaging device with the processing circuit. The processing circuit is configured to determine when a change is required in a first data protection configuration that protects first image data transmitted over a first data communication link, and determine a second data protection configuration to be used when second image data is transmitted from a first imaging device over the first data communication link to an image processing circuit. The first data protection configuration or the second data protection configuration provides a partial integrity mode of data protection for frames of image data transmitted over the first data communication link. The partial integrity mode protects some, but not all frames of image data transmitted over the first data communication link using a message authentication code.

公开(公告)号：US20240248870A1

公开(公告)日：2024-07-25

申请号：US18157000

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Umesh SRIKANTIAH ,  Lalan Jee MISHRA ,  Francesco GATTA ,  Richard Dominic WIETFELDT

IPC: G06F13/42

CPC classification number: G06F13/4291

Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.

公开(公告)号：US20230267085A1

公开(公告)日：2023-08-24

申请号：US17677731

申请日：2022-02-22

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/12 ,  H04L12/40

CPC classification number: G06F13/362 ,  G06F13/4282 ,  G06F1/12 ,  H04L12/40

Abstract: An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.

公开(公告)号：US20230056239A1

公开(公告)日：2023-02-23

申请号：US17978923

申请日：2022-11-01

Applicant: QUALCOMM INCORPORATED

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  James Lionel PANIAN ,  Georgios Konstantinos PAPARRIZOS

IPC: H01R13/66 ,  H01R24/28 ,  H01B7/42 ,  H01R25/00 ,  H01R13/533

Abstract: Thermal mitigation features may be included in a Universal Serial Bus (USB) cable assembly or in the USB receptacle portion of a device. In one aspect, one or both ends of a USB cable jacket may have greater thermal conductivity than the portion between them. The portion having the greater thermal conductivity may dissipate excess heat from the cable into the environment. In another aspect, a USB cable connector or the USB receptacle portion of a device may include a thermoelectric heat pump. The thermoelectric heat pump may move excess heat from the cable assembly or receptacle into a portion of the cable assembly or device that dissipates the heat into the environment.

公开(公告)号：US20220222200A1

公开(公告)日：2022-07-14

申请号：US17148953

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/362 ,  G06F9/30

Abstract: Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

公开(公告)号：US20220091952A1

公开(公告)日：2022-03-24

申请号：US17027541

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Lalan Jee MISHRA

IPC: G06F11/30 ,  G06F11/10 ,  G06F11/07 ,  G06F13/42

Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

公开(公告)号：US20220066978A1

公开(公告)日：2022-03-03

申请号：US17005158

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Umesh SRIKANTIAH ,  Karthik MANIVANNAN

IPC: G06F13/42

Abstract: Systems, methods, and apparatus improve accuracy of trigger timing by compensating for clock pulses that are suppressed when datagrams are transmitted over a serial bus. A method includes configuring an initial value of an output of a counter in a timing circuit, enabling the counter to count pulses in a clock signal received from the serial bus, determining that a datagram is being transmitted on the serial bus while the counter is counting the pulses in the clock signal, providing a timing value that represents a current value of the output of the counter adjusted to compensate for one or more clock pulses suppressed during transmission of the datagram, and providing a trigger when the timing value reaches a maximum value or a minimum value. The counter may be a countdown counter and two clock pulses may be suppressed for each sequence start condition transmitted on the serial bus.

公开(公告)号：US20200097434A1

公开(公告)日：2020-03-26

申请号：US16142456

申请日：2018-09-26

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F1/10

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes including a mode that encodes data in a clock signal. A method includes providing a clock signal that controls timing of transactions conducted over a serial bus, transmitting a first pair of data bytes at double data rate over a first wire of the serial bus in a first transaction, modulating the clock signal during the first transaction to provide a modulated clock signal that encodes at least one additional data byte, and transmitting the modulated clock signal over a second wire of the serial bus during the first transaction.

公开(公告)号：US20200081859A1

公开(公告)日：2020-03-12

申请号：US16546495

申请日：2019-08-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/38 ,  G06F13/362

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.