公开(公告)号：US20250062758A1

公开(公告)日：2025-02-20

申请号：US18449554

申请日：2023-08-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

IPC: H03K5/24 ,  H03K3/037 ,  H03K3/356

Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

公开(公告)号：US20240281401A1

公开(公告)日：2024-08-22

申请号：US18171264

申请日：2023-02-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Umesh SRIKANTIAH ,  Francesco GATTA ,  Christopher Kong Yee CHUN

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4022 ,  G06F2213/0018

Abstract: A subordinate device participates in address assignment through iterative communication with a host device. The subordinate device receives a first broadcast command over a multidrop serial bus, decouples a daisy chain input of the subordinate device from a daisy chain output of the subordinate device, receives a second broadcast command over the multidrop serial bus, responds to the second broadcast command when a signal received through the daisy chain input is in an active state, ignores the second broadcast command when the signal received through the daisy chain input is in an inactive state, and ignores subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the subordinate device using an address provided in the second broadcast command, and coupling the daisy chain input of the subordinate device to the daisy chain output of the subordinate device.

公开(公告)号：US20190286587A1

公开(公告)日：2019-09-19

申请号：US16262267

申请日：2019-01-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Helena Deirdre O'SHEA ,  Wolfgang ROETHIG ,  Christopher Kong Yee CHUN ,  ZhenQi CHEN ,  Scott DAVENPORT ,  Chiew-Guan TAN ,  Wilson CHEN ,  Umesh SRIKANTIAH

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

公开(公告)号：US20240311228A1

公开(公告)日：2024-09-19

申请号：US18183833

申请日：2023-03-14

Applicant: QUALCOMM Incorporated

Inventor： Umesh SRIKANTIAH ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Boris ALPIN ,  Francesco GATTA

IPC: G06F11/07 ,  G06F13/42

CPC classification number: G06F11/0793 ,  G06F11/0757 ,  G06F11/0772 ,  G06F13/4291

Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

公开(公告)号：US20210096182A1

公开(公告)日：2021-04-01

申请号：US16589968

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti CHAKRABORTY ,  Umesh SRIKANTIAH ,  Rachana ROUT

IPC: G01R31/317 ,  G01R31/3177

Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.

公开(公告)号：US20240241853A1

公开(公告)日：2024-07-18

申请号：US18155499

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Francesco GATTA ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4295 ,  G06F13/24

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

公开(公告)号：US20240089195A1

公开(公告)日：2024-03-14

申请号：US17943565

申请日：2022-09-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT ,  Radu PITIGOI-ARON

IPC: H04L45/24

CPC classification number: H04L45/245 ,  H04L12/40

Abstract: A multi-port data communication apparatus includes a first port having a first physical interface circuit configured to couple the multi-port data communication apparatus to a first serial bus that has a first line and a second line, a second port having a second physical interface circuit configured to couple the multi-port data communication apparatus to a second serial bus that has a first line and a second line, and a controller. The controller is configured to use the first port during a first transaction restricted to transmissions over the first serial bus and use the first port and the second port in a second transaction in which data is transmitted over the second line of the first serial bus and the second line of the second serial bus in accordance with timing provided by a clock signal transmitted over the first line of the first serial bus.

公开(公告)号：US20240012778A1

公开(公告)日：2024-01-11

申请号：US17861886

申请日：2022-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Francesco GATTA ,  Muhlis Kenan OZEL ,  Richard Dominic WIETFELDT

IPC: G06F13/40 ,  H04L7/00 ,  H04L7/04

CPC classification number: G06F13/4068 ,  H04L7/0066 ,  H04L7/042 ,  H04L7/0087 ,  G06F2213/40

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

公开(公告)号：US20210081348A1

公开(公告)日：2021-03-18

申请号：US17003724

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

公开(公告)号：US20210081340A1

公开(公告)日：2021-03-18

申请号：US17003697

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

IPC: G06F13/20 ,  H04L29/08 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.