公开(公告)号：US20240311228A1

公开(公告)日：2024-09-19

申请号：US18183833

申请日：2023-03-14

Applicant: QUALCOMM Incorporated

Inventor： Umesh SRIKANTIAH ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Boris ALPIN ,  Francesco GATTA

IPC: G06F11/07 ,  G06F13/42

CPC classification number: G06F11/0793 ,  G06F11/0757 ,  G06F11/0772 ,  G06F13/4291

Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

公开(公告)号：US20210303489A1

公开(公告)日：2021-09-30

申请号：US16829163

申请日：2020-03-25

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F13/20 ,  G06F13/42

Abstract: Systems, methods, and apparatus increase the number of slave devices that can be connected to a serial bus. The bus protocol may be an RFFE protocol, an SPMI protocol, an I3C protocol or another protocol usable on a serial bus. In various aspects of the disclosure, a method performed at a device coupled to a serial bus includes receiving a first datagram at a slave device coupled to a serial bus, where the first datagram includes a 4-bit broadcast address indicative of a broadcast datagram, a first command directed to an invalid register address, and a payload, determining an encapsulation protocol associated with the invalid register address, and responding to a second command carried in the payload when an 8-bit slave address in the payload matches an 8-bit slave identifier allocated to the slave device.

公开(公告)号：US20210265786A1

公开(公告)日：2021-08-26

申请号：US16798238

申请日：2020-02-21

Applicant: QUALCOMM INCORPORATED

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  James lionel PANIAN ,  Georgios Konstantinos PAPARRIZOS

IPC: H01R13/66

Abstract: Thermal mitigation features may be included in a Universal Serial Bus (USB) cable assembly or in the USB receptacle portion of a device. In one aspect, one or both ends of a USB cable jacket may have greater thermal conductivity than the portion between them. The portion having the greater thermal conductivity may dissipate excess heat from the cable into the environment. In another aspect, a USB cable connector or the USB receptacle portion of a device may include a thermoelectric heat pump. The thermoelectric heat pump may move excess heat from the cable assembly or receptacle into a portion of the cable assembly or device that dissipates the heat into the environment.

公开(公告)号：US20200042248A1

公开(公告)日：2020-02-06

申请号：US16508136

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F3/06 ,  G06F13/42 ,  G06F9/30

Abstract: Systems, methods, and apparatus for increasing register space on a slave device are described. A method performed at a device coupled to a serial bus includes receiving a datagram from a serial bus, the datagram including a command directed to a first register address in a first page of registers, writing data in a payload of the datagram to a second register address in a second page of registers when the command is a write command, and reading data from the second register address in the second page of registers when the command is a read command. The second register address is identified in the datagram when the command is a write command.

公开(公告)号：US20200034158A1

公开(公告)日：2020-01-30

申请号：US16507947

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic WIETFELDT ,  Lalan Jee MISHRA

IPC: G06F9/445 ,  G06F13/42 ,  G06F1/10

Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

公开(公告)号：US20200033908A1

公开(公告)日：2020-01-30

申请号：US16507904

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F1/10 ,  G06F13/362 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency are described. Clock-cycle overhead associated with the transmission of trigger activation information may be reduced through the use of optimized datagram structures for register-configurable trigger activation mechanisms. A first mechanism defines a command code with a first Trigger-Activation datagram, and a second mechanism defines a command code with a second Trigger-Activation datagram that uses a 4-bit Magic-ID and eliminates 18 clock cycles from the conventional Extended Register Write datagram structure. A method performed at a device coupled to a serial bus includes generating a datagram that does not have an address field, populating a data payload of the datagram with trigger activation information directed to a plurality of slave devices coupled to a serial bus, and transmitting the datagram over the serial bus. Transmission of the datagram serves as a trigger that causes a configuration change in at least one slave device.

公开(公告)号：US20190073327A1

公开(公告)日：2019-03-07

申请号：US15698191

申请日：2017-09-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Helena Deirdre O'SHEA ,  Richard Dominic WIETFELDT

IPC: G06F13/28 ,  H04W28/06 ,  H04L29/06

CPC classification number: G06F13/28 ,  G06F13/4291 ,  H04L69/04 ,  H04W28/06

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

公开(公告)号：US20180357067A1

公开(公告)日：2018-12-13

申请号：US15994955

申请日：2018-05-31

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F9/4401 ,  G06F1/10

CPC classification number: G06F9/4403 ,  G06F1/10 ,  G06F1/24

Abstract: Systems, methods, and apparatus for signaling in-band hardware resets over a serial communication link are provided. A sending device obtains a reference value for configuring a pulse to be sent to the receiving device, configures the pulse to have a logic state (low logic state or high logic state) for a time period based on the reference value, and sends the pulse on a data line between the sending device and a receiving device to indicate the in-band hardware reset to the receiving device. A receiving device receives a pulse on a data line between a sending device and the receiving device, compares a time period of a logic state (low logic state or high logic state) of the pulse to a reference value, detects whether the pulse indicates the in-band hardware reset based on comparison, and performs the in-band hardware reset if the pulse indicates the hardware reset.

公开(公告)号：US20180329838A1

公开(公告)日：2018-11-15

申请号：US15960356

申请日：2018-04-23

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Christopher Kong Yee CHUN ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD

IPC: G06F13/16

CPC classification number: G06F13/1605 ,  G06F13/1673 ,  G06F13/4291 ,  G06F2213/0016

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

公开(公告)号：US20180060272A1

公开(公告)日：2018-03-01

申请号：US15803639

申请日：2017-11-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Helena Deirdre O'SHEA ,  ZhenQi CHEN ,  Wolfgang ROETHIG

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F21/85

CPC classification number: G06F13/4286 ,  G06F13/102 ,  G06F13/16 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4022 ,  G06F21/85

Abstract: Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.