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    REAL-TIME CONTROL COMPLIANT RADIO FREQUENCY COEXISTENCE MANAGEMENT BUS
    2.
    发明申请
    REAL-TIME CONTROL COMPLIANT RADIO FREQUENCY COEXISTENCE MANAGEMENT BUS 有权

    公开(公告)号：US20220083483A1

    公开(公告)日：2022-03-17

    申请号：US17024258

    申请日：2020-09-17

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Mohit Kishore PRASAD ,  Richard Dominic WIETFELDT ,  Irfan KHAN

    IPC: G06F13/20 ,  G06F13/42

    Abstract: Systems, methods, and apparatus for multi-drop coexistence management are described. A data communication apparatus has a bus interface that couples the data communication apparatus to a serial bus and a controller configured to determine that a datagram received from the serial bus is addressed to a register address corresponding to a coexistence management identifier, activate a line driver of the bus interface circuit that is coupled to a data line of the serial bus during a portion of a first payload of the datagram when one or more coexistence management messages are ready for sending from the slave device, where the portion of the first payload of the datagram is allocated for use of the apparatus, and transmit a first coexistence management message in the portion of the first payload of the datagram that is allocated for use of the data communication apparatus.

    SLAVE MASTER-WRITE/READ DATAGRAM PAYLOAD EXTENSION
    3.
    发明申请
    SLAVE MASTER-WRITE/READ DATAGRAM PAYLOAD EXTENSION 审中-公开

    公开(公告)号：US20200073847A1

    公开(公告)日：2020-03-05

    申请号：US16678827

    申请日：2019-11-08

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Mohit Kishore PRASAD ,  Richard Dominic WIETFELDT ,  Christopher Kong Yee CHUN

    IPC: G06F13/42 ,  G06F13/10 ,  G06F13/16 ,  G06F13/20

    Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

    HARDWARE EVENT PRIORITY SENSITIVE PROGRAMMABLE TRANSMIT WAIT-WINDOW FOR VIRTUAL GPIO FINITE STATE MACHINE
    4.
    发明申请
    HARDWARE EVENT PRIORITY SENSITIVE PROGRAMMABLE TRANSMIT WAIT-WINDOW FOR VIRTUAL GPIO FINITE STATE MACHINE 审中-公开

    公开(公告)号：US20180329857A1

    公开(公告)日：2018-11-15

    申请号：US15974204

    申请日：2018-05-08

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4282 ,  G06F13/4068 ,  G06F13/4291 ,  G06F2213/0016

    Abstract: Systems, apparatus, methods and techniques that can provide optimized low-latency communications between different devices such that GPIO signals may be carried as virtual signals. A virtual GPIO finite state machine in a first device is provided that can consolidate GPIO-related events by initiating a wait period after a first-occurring event and that has a duration selected to permit one or more later-occurring events to be detected before transmission of virtual GPIO data over a data communication bus to a second device. One method may include initiating a wait period after detecting a first change in GPIO state, refraining from transmitting virtual GPIO data during the wait period, detecting occurrence of a second change in GPIO state during the wait period, and transmitting virtual GPIO data corresponding to the first and second changes in GPIO state over the serial bus after the wait period has expired.

    INTEGRAL SUPER-CAPACITOR FOR LOW POWER APPLICATIONS
    5.
    发明申请
    INTEGRAL SUPER-CAPACITOR FOR LOW POWER APPLICATIONS 有权

    公开(公告)号：US20210345481A1

    公开(公告)日：2021-11-04

    申请号：US16862130

    申请日：2020-04-29

    Applicant: QUALCOMM Incorporated

    Inventor： Mohit Kishore PRASAD ,  Lalan Jee MISHRA

    IPC: H05K1/02 ,  H01G4/018 ,  H02J7/00

    Abstract: Certain aspects of the present disclosure generally relate to an electronic device with a circuit board having one or more super-capacitors implemented therein using the layers of the circuit board. An example electronic device generally includes a circuit board having a capacitive element implemented therein, wherein the capacitive element comprises a first conductive layer, a second conductive layer disposed below the first conductive layer, and a solid dielectric material disposed between the first and second conductive layers, wherein the dielectric material has a high dielectric constant greater than 10,000 (1E4); and an integrated circuit coupled to the circuit board.

    FUNCTION-SPECIFIC COMMUNICATION ON A MULTI-DROP BUS FOR COEXISTENCE MANAGEMENT
    6.
    发明申请
    FUNCTION-SPECIFIC COMMUNICATION ON A MULTI-DROP BUS FOR COEXISTENCE MANAGEMENT 审中-公开

    公开(公告)号：US20190227962A1

    公开(公告)日：2019-07-25

    申请号：US16193853

    申请日：2018-11-16

    Applicant: QUALCOMM Incorporated

    Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Gary CHANG

    IPC: G06F13/20 ,  G06F13/42

    CPC classification number: G06F13/20 ,  G06F13/4282

    Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

    VERSATILE CONTROL MESSAGING SCHEME FOR RADIO COEXISTENCE MANAGEMENT
    8.
    发明申请
    VERSATILE CONTROL MESSAGING SCHEME FOR RADIO COEXISTENCE MANAGEMENT 有权

    公开(公告)号：US20220004513A1

    公开(公告)日：2022-01-06

    申请号：US16920150

    申请日：2020-07-02

    Applicant: QUALCOMM Incorporated

    Inventor： Mohit Kishore PRASAD ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

    IPC: G06F13/362 ,  G06F13/42

    Abstract: An apparatus includes an interface circuit adapted to couple the apparatus to a serial bus, a slot counter, and a processor. The slot counter may be configured to monitor a radio frequency coexistence management cycle that includes a plurality of time slots. The processor may be configured to transmit a first datagram through the interface circuit during a first time slot in the plurality of time slots. The apparatus may be uniquely permitted to initiate transactions over the serial bus during the first time slot. The processor may be further configured to participate in an arbitration procedure during a second time slot in the plurality of time slots. More than one device coupled to the serial bus may be permitted to initiate transactions in the second time slot.

    ARCHITECTURE FOR CONSOLIDATING MULTIPLE SOURCES OF LOW-BANDWIDTH DATA OVER A SERIAL BUS
    9.
    发明申请
    ARCHITECTURE FOR CONSOLIDATING MULTIPLE SOURCES OF LOW-BANDWIDTH DATA OVER A SERIAL BUS 审中-公开

    公开(公告)号：US20190227971A1

    公开(公告)日：2019-07-25

    申请号：US16193731

    申请日：2018-11-16

    Applicant: QUALCOMM Incorporated

    Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Joaquin ROMERA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A method performed at a first device coupled to a serial bus includes receiving first coexistence information directed to a second device, selecting a communication link to carry the first coexistence information to the second device, generating a first datagram that includes the first coexistence information, transmitting the first datagram to the second device over a point-to-point link in a first mode of operation, and transmitting the first datagram to the second device over a multi-drop serial bus in a second mode of operation. The first datagram may be configured according to a protocol associated with the communication link selected to carry the first coexistence information.

    LOW POWER PCIE
    10.
    发明申请
    LOW POWER PCIE 审中-公开

    公开(公告)号：US20190107882A1

    公开(公告)日：2019-04-11

    申请号：US16155824

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  James Lionel PANIAN ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Shaul Yohai YIFRACH

    IPC: G06F1/32 ,  G06F13/10 ,  G06F13/40

    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

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