公开(公告)号：US20220066978A1

公开(公告)日：2022-03-03

申请号：US17005158

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Umesh SRIKANTIAH ,  Karthik MANIVANNAN

IPC: G06F13/42

Abstract: Systems, methods, and apparatus improve accuracy of trigger timing by compensating for clock pulses that are suppressed when datagrams are transmitted over a serial bus. A method includes configuring an initial value of an output of a counter in a timing circuit, enabling the counter to count pulses in a clock signal received from the serial bus, determining that a datagram is being transmitted on the serial bus while the counter is counting the pulses in the clock signal, providing a timing value that represents a current value of the output of the counter adjusted to compensate for one or more clock pulses suppressed during transmission of the datagram, and providing a trigger when the timing value reaches a maximum value or a minimum value. The counter may be a countdown counter and two clock pulses may be suppressed for each sequence start condition transmitted on the serial bus.