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281 条记录 (耗时 0.036 秒)

    Protective case for a watch
    61.
    外观设计
    Protective case for a watch 有权

    公开(公告)号：USD1022753S1

    公开(公告)日：2024-04-16

    申请号：US29900511

    申请日：2023-08-22

    申请人： Wei Huang

    设计人： Wei Huang

    摘要： FIG. 1 is a front perspective view of a protective case for a watch, showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left side view thereof;
    FIG. 5 is a right side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof;
    FIG. 8 is a split state diagram thereof; and,
    FIG. 9 is a second split state diagram thereof.
    The broken lines in the drawings illustrate the portions of the protective case for a watch, which form no part of the claimed design.

    Wireless microphone receiver
    62.
    外观设计
    Wireless microphone receiver 有权

    公开(公告)号：USD1020708S1

    公开(公告)日：2024-04-02

    申请号：US29914516

    申请日：2023-10-18

    申请人： Wei Huang

    设计人： Wei Huang

    摘要： FIG. 1 is a front and top perspective view of a wireless microphone receiver showing my new design;
    FIG. 2 is a front view thereof.
    FIG. 3 is a rear view thereof.
    FIG. 4 is a left side view thereof, shown enlarged in scale.
    FIG. 5 is a right side view thereof, shown enlarged in scale.
    FIG. 6 is a top view thereof.
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is rear and bottom perspective view thereof.
    The broken lines in the drawings depict portions of the wireless microphone receiver that form no part of the claimed design.

    Lunch bag
    64.
    外观设计
    Lunch bag 有权

    公开(公告)号：USD856099S1

    公开(公告)日：2019-08-13

    申请号：US29640489

    申请日：2018-03-14

    申请人： Wei Huang

    设计人： Wei Huang

    3D CHIP STACK WITH INTEGRATED VOLTAGE REGULATION
    65.
    发明申请
    3D CHIP STACK WITH INTEGRATED VOLTAGE REGULATION 审中-公开

    公开(公告)号：US20190103153A1

    公开(公告)日：2019-04-04

    申请号：US15724980

    申请日：2017-10-04

    申请人： Wei Huang

    发明人： Wei Huang

    IPC分类号： G11C11/4074 ,  H01L27/06 ,  G11C5/14 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L27/02

    摘要： Various 3D chip stacks with integrated voltage regulation are disclosed. In one aspect, a semiconductor chip device includes a 3D chip stack that includes a first semiconductor chip that has a first integrated voltage regulator, a second semiconductor chip that has a second integrated voltage regulator and at least one additional semiconductor chip positioned between the first semiconductor chip and the second semiconductor chip. At least one of the first semiconductor chip and the second semiconductor chip is configured to supply a regulated voltage to the at least one additional semiconductor chip.

    On-chip control of thermal cycling
    66.
    发明授权
    On-chip control of thermal cycling 有权

    公开(公告)号：US10049957B2

    公开(公告)日：2018-08-14

    申请号：US13040094

    申请日：2011-03-03

    申请人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Elmootazbellah Nabil Elnozahy ,  Wei Huang

    发明人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Elmootazbellah Nabil Elnozahy ,  Wei Huang

    IPC分类号： H01L23/34

    摘要： A method, system, and computer program product for on-chip control of thermal cycling in an integrated circuit (IC) are provided in the illustrative embodiments. A first circuit is configured on the IC for adjusting a first voltage being applied to a first part of the IC. A first temperature of the first part is measured at a first time. A determination is made that the first temperature is outside a temperature range defined by an upper temperature threshold and a lower temperature threshold. The first voltage is adjusted by reducing the first voltage when the first temperature exceeds the upper temperature threshold and by increasing the first voltage when the first temperature is below the lower temperature threshold, thereby causing the first temperature of the first part to attain a value within the temperature range.

    Global synchronization method and system based on packet switching system
    69.
    发明授权
    Global synchronization method and system based on packet switching system 有权

    公开(公告)号：US09391766B2

    公开(公告)日：2016-07-12

    申请号：US14369332

    申请日：2011-12-27

    申请人： Wei Huang

    发明人： Wei Huang

    IPC分类号： H04J3/06 ,  H04L7/00 ,  H04L12/931

    CPC分类号： H04L7/0016 ,  H04J3/0658 ,  H04L49/40

    摘要： A global synchronization method based on a packet switching system includes that: a reference chip is selected; and each chip calibrates its own timer by taking the reference chip as a reference, wherein each chip sends a zero-point pulse or zero-point pulse cell to each high-speed link (serdes) connected with the chip, and feeds back a calibration cell in response to a zero-point pulse or zero-point pulse cell received through each high-speed link. Accordingly, a global synchronization system based on a packet switching system is also disclosed. The disclosure reduces the packet loss rate and increases the accuracy of calibration.