公开(公告)号：US20230125798A1

公开(公告)日：2023-04-27

申请号：US18069033

申请日：2022-12-20

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/1018 ,  G06F13/16

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20220342806A1

公开(公告)日：2022-10-27

申请号：US17519284

申请日：2021-11-04

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US11042373B2

公开(公告)日：2021-06-22

申请号：US16928752

申请日：2020-07-14

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari ,  Gerard R. Williams, III

IPC: G06F9/30 ,  G06F17/16

Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

公开(公告)号：US10831484B1

公开(公告)日：2020-11-10

申请号：US16524490

申请日：2019-07-29

Applicant: Apple Inc.

Inventor： Yannick L. Sierra ,  Jeffry E. Gonion ,  Thomas Roche ,  Jerrold V. Hauck

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/14

Abstract: In an embodiment, a processor includes hardware circuitry and/or supports instructions which may be used to detect that a return address or jump address has been modified since it was written to memory. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified address. In an embodiment, the processor may perform a cryptographic sign operation on the return address/jump address before writing the signed return address/jump address to memory and the signature may be verified before the address is used as a return target or jump target. Security of the system may be improved by foiling ROP/JOP attacks.

公开(公告)号：US20190294541A1

公开(公告)日：2019-09-26

申请号：US16436635

申请日：2019-06-10

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Charles E. Tucker ,  Jeffry E. Gonion ,  Gerard R. Williams, III ,  Chris Cheng-Chieh Lee

IPC: G06F12/08 ,  H03M7/30 ,  G06F12/0886

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

公开(公告)号：US20190294441A1

公开(公告)日：2019-09-26

申请号：US16423702

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US10409600B1

公开(公告)日：2019-09-10

申请号：US15202269

申请日：2016-07-05

Applicant: Apple Inc.

Inventor： Yannick L. Sierra ,  Jeffry E. Gonion ,  Thomas Roche ,  Jerrold V. Hauck

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/14

Abstract: In an embodiment, a processor includes hardware circuitry and/or supports instructions which may be used to detect that a return address or jump address has been modified since it was written to memory. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified address. In an embodiment, the processor may perform a cryptographic sign operation on the return address/jump address before writing the signed return address/jump address to memory and the signature may be verified before the to address is used as a return target or jump target. Security of the system may be improved by foiling ROP/JOP attacks.

公开(公告)号：US20190129719A1

公开(公告)日：2019-05-02

申请号：US15800342

申请日：2017-11-01

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3887 ,  G06F17/16

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US10275365B1

公开(公告)日：2019-04-30

申请号：US15232456

申请日：2016-08-09

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: H04L9/32 ,  G06F12/14

Abstract: In an embodiment, a processor includes hardware circuitry and/or supports instructions which may cryptographically sign a pointer and its associated capabilities. When the pointer is used to perform a memory operation (read or write), the signed pointer may be authenticated to ensure that unauthorized modification of the pointer or capabilities has not occurred. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent the memory operation from completing.

公开(公告)号：US09817663B2

公开(公告)日：2017-11-14

申请号：US14218287

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3838

Abstract: Systems, apparatuses and methods for utilizing enhanced macro scalar predicate operations which take enhanced predicate operands that designate the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition of the instruction. This enables additional parallelism when processing smaller-sized data. The instruction performs the requested operation on the elements specified by the enhanced control predicate, assuming an element-width also specified by the enhanced control predicate, and returns the result as an enhanced predicate of the same element width.