公开(公告)号：US10831484B1

公开(公告)日：2020-11-10

申请号：US16524490

申请日：2019-07-29

Applicant: Apple Inc.

Inventor： Yannick L. Sierra ,  Jeffry E. Gonion ,  Thomas Roche ,  Jerrold V. Hauck

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/14

Abstract: In an embodiment, a processor includes hardware circuitry and/or supports instructions which may be used to detect that a return address or jump address has been modified since it was written to memory. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified address. In an embodiment, the processor may perform a cryptographic sign operation on the return address/jump address before writing the signed return address/jump address to memory and the signature may be verified before the address is used as a return target or jump target. Security of the system may be improved by foiling ROP/JOP attacks.

公开(公告)号：US10409600B1

公开(公告)日：2019-09-10

申请号：US15202269

申请日：2016-07-05

Applicant: Apple Inc.

Inventor： Yannick L. Sierra ,  Jeffry E. Gonion ,  Thomas Roche ,  Jerrold V. Hauck

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/14

Abstract: In an embodiment, a processor includes hardware circuitry and/or supports instructions which may be used to detect that a return address or jump address has been modified since it was written to memory. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified address. In an embodiment, the processor may perform a cryptographic sign operation on the return address/jump address before writing the signed return address/jump address to memory and the signature may be verified before the to address is used as a return target or jump target. Security of the system may be improved by foiling ROP/JOP attacks.