公开(公告)号：US6154821A

公开(公告)日：2000-11-28

申请号：US38358

申请日：1998-03-10

申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/00

CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C7/20 ,  G11C8/12 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02B60/1235

摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

摘要翻译： 提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。 确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。 随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。 然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。 在确定每个DRAM器件的响应时间并且使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合 总线等于最长响应时间。 通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

公开(公告)号：US6075744A

公开(公告)日：2000-06-13

申请号：US169376

申请日：1998-10-09

申请人： Ely K. Tsern ,  Richard M. Barth ,  Paul G. Davis ,  Craig E. Hampel

发明人： Ely K. Tsern ,  Richard M. Barth ,  Paul G. Davis ,  Craig E. Hampel

IPC分类号： G11C8/08 ,  G11C11/406 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C8/08 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.

摘要翻译： 一种用于将通过接口总线的通信开销减少到用于刷新操作的存储器设备的方法。 这是通过刷新多个银行来响应单个命令来完成的。 与普通存储器访问相比，通过改变在刷新操作期间的行感测和行预充电电流的电流分布，可实现多重量刷新。 与普通内存访问不同，不需要数据，不需要快速访问时间。 这允许使用不同的电路来传播电流来驱动电流以减少电流尖峰。 扩展电流仍然保持在正常内存访问的时间内。

公开(公告)号：US6075730A

公开(公告)日：2000-06-13

申请号：US169729

申请日：1998-10-09

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/229

摘要： A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

摘要翻译： 存储器件包括具有控制引脚和双向数据引脚的互连。 内存核心存储数据。 存储器接口电路连接到互连和存储器核。 存储器接口电路包括延迟电路，以在存储器核心写入事务期间建立写入延迟，使得存储器核心写入事务具有基本上等同于存储器核心读取事务的处理时间。 延迟电路将存储器核心写入事务延迟一段时间，该时间对应于信号在互连上行进所需的时间。

公开(公告)号：US5956284A

公开(公告)日：1999-09-21

申请号：US167632

申请日：1998-10-06

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

公开(公告)号：US08560797B2

公开(公告)日：2013-10-15

申请号：US13421701

申请日：2012-03-15

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasborro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasborro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

摘要翻译： 一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址 以指示要写入第一数据的DRAM中的存储器核的列位置。 该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。 如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。 接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

公开(公告)号：US08296540B2

公开(公告)日：2012-10-23

申请号：US12036598

申请日：2008-02-25

申请人： Bruno Werner Garlepp ,  Pak Shing Chau ,  Kevin S. Donnelly ,  Clemenz Portmann ,  Donald C. Stark ,  Stefanos Sidiropoulos ,  Richard M. Barth ,  Paul G. Davis ,  Ely K. Tsern

发明人： Bruno Werner Garlepp ,  Pak Shing Chau ,  Kevin S. Donnelly ,  Clemenz Portmann ,  Donald C. Stark ,  Stefanos Sidiropoulos ,  Richard M. Barth ,  Paul G. Davis ,  Ely K. Tsern

IPC分类号： G11C7/04 ,  G01K1/00 ,  G01K3/00 ,  G01K15/00 ,  G01M1/38 ,  G06F3/00 ,  G06F12/00

CPC分类号： G11C7/1048 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.

摘要翻译： 提供了一种用于调整存储器系统的性能的方法和装置。 存储器系统包括主设备和从设备。 存储器通道将主设备耦合到从设备，使得从设备经由存储器通道从主设备接收系统操作信息。 从设备还包括从设备内的调谐电路，从而提高存储系统的性能。

公开(公告)号：US08248884B2

公开(公告)日：2012-08-21

申请号：US12975322

申请日：2010-12-21

申请人： Ely K. Tsern ,  Richard M. Barth ,  Craig E. Hampel ,  Donald C. Stark

发明人： Ely K. Tsern ,  Richard M. Barth ,  Craig E. Hampel ,  Donald C. Stark

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G11C7/1039 ,  G11C7/1072 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A memory device includes a clock receiver, a command interface, and a data interface separate from the command interface. A memory controller provides the command interface with a command that specifies a write operation. After a programmable latency period transpires from providing the command, data associated with the write operation is provided to the data interface by the memory controller. The memory controller provides power mode information that controls transitions between a plurality of power modes, where for each power mode of the plurality of power modes, less power is consumed than the amount of power consumed during the write operation. The power modes include a mode in which the clock receiver is on and the data interface is off; and a mode in which the clock receiver is off and the data interface is off.

摘要翻译： 存储器件包括时钟接收器，命令接口和与命令接口分开的数据接口。 存储器控制器为命令接口提供指定写入操作的命令。 在从提供命令开始可编程的等待时间之后，由写入操作相关联的数据由存储器控制器提供给数据接口。 存储器控制器提供功率模式信息，其控制多个功率模式之间的转换，其中对于多个功率模式的每个功率模式，消耗的功率比在写入操作期间消耗的功率量少。 功率模式包括时钟接收器接通和数据接口关闭的模式; 以及时钟接收器关闭且数据接口关闭的模式。

公开(公告)号：US20120173811A1

公开(公告)日：2012-07-05

申请号：US13421753

申请日：2012-03-15

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.

摘要翻译： 一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。 第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。 该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。 该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。 第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

公开(公告)号：US08019958B2

公开(公告)日：2011-09-13

申请号：US12875483

申请日：2010-09-03

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarre ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarre ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

摘要翻译： 在控制存储器件的方法中，以下是通过第一组互连资源传送的：指定一行存储器单元的激活的第一命令; 指定写操作的第二命令，其中写数据被写入行; 指定在写入数据写入之后是否发生预充电的一点; 以及指定是否将为写入操作发布数据掩码信息的代码。 如果代码指定信息将被发出，则在传送代码之后，通过第一组互连资源传送指定是否选择性地写入写入数据的部分的信息。 要写入与写入操作相关的写入数据通过与第一组互连资源分开的第二组互连资源传送。

公开(公告)号：US07986584B2

公开(公告)日：2011-07-26

申请号：US12608209

申请日：2009-10-29

申请人： Ely K. Tsern ,  Richard M. Barth ,  Craig E. Hampel ,  Donald C. Stark

发明人： Ely K. Tsern ,  Richard M. Barth ,  Craig E. Hampel ,  Donald C. Stark

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G11C7/1039 ,  G11C7/1072 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。 数据接口与第一个接口分开。 第二个接口与第一个接口和数据接口分开。 存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。 在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。