公开(公告)号：US20080157094A1

公开(公告)日：2008-07-03

申请号：US11966056

申请日：2007-12-28

Applicant: JIN-WOOK SEO ,  Byoung-Keon Park ,  Tae-Hoon Yang ,  Ki-Yong Lee

Inventor： JIN-WOOK SEO ,  Byoung-Keon Park ,  Tae-Hoon Yang ,  Ki-Yong Lee

IPC: H01L29/04 ,  H01L21/336

CPC classification number: H01L29/78675 ,  H01L27/1277 ,  H01L27/3244 ,  H01L29/04 ,  H01L29/66757

Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a source region, a drain region and a channel region, and made of a polycrystalline silicon layer; a gate electrode disposed to correspond to the channel region of the semiconductor layer; a gate insulating layer disposed between the semiconductor layer and the gate electrode; and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer, respectively, wherein the polycrystalline silicon layer comprises a plurality of regions having different Raman spectrum peaks from each other.

Abstract translation: 薄膜晶体管包括：基板; 设置在所述基板上的半导体层，包括源极区域，漏极区域和沟道区域，并且由多晶硅层制成; 设置成对应于半导体层的沟道区的栅电极; 设置在所述半导体层和所述栅极之间的栅极绝缘层; 以及分别与半导体层的源极和漏极区电连接的源极和漏极，其中多晶硅层包括彼此具有不同拉曼光谱峰的多个区域。

公开(公告)号：US20070284581A1

公开(公告)日：2007-12-13

申请号：US11741307

申请日：2007-04-27

Applicant: Tae-hoon Yang ,  Ki-yong Lee ,  Jin-wook Seo ,  Byoung-keon Park

Inventor： Tae-hoon Yang ,  Ki-yong Lee ,  Jin-wook Seo ,  Byoung-keon Park

IPC: H01L21/335 ,  H01L29/04

CPC classification number: H01L29/66757 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/1277

Abstract: A method of fabricating a p-type thin film transistor (TFT) includes: performing a first annealing process on a substrate to diffuse a metal catalyst through a capping layer into a surface of an amorphous silicon layer, and to crystallize the amorphous silicon layer to a polycrystalline silicon layer due to the diffused metal catalyst; removing the capping layer; patterning the polycrystalline silicon layer to form a semiconductor layer; forming a gate insulating layer and a gate electrode on the substrate; implanting p-type impurity ions into the semiconductor layer; and implanting a gettering material into the semiconductor layer and performing a second annealing process to remove the metal catalyst. Herein, the p-type impurity ions are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the gettering material is implanted at a dose of 1×1011/cm2 to 3×1015/cm2.

Abstract translation: 一种制造p型薄膜晶体管（TFT）的方法包括：在衬底上进行第一退火处理，将金属催化剂通过覆盖层扩散到非晶硅层的表面中，并将非晶硅层结晶成 由于扩散金属催化剂而导致的多晶硅层; 去除覆盖层; 图案化多晶硅层以形成半导体层; 在基板上形成栅极绝缘层和栅电极; 将p型杂质离子注入到半导体层中; 以及将吸气材料注入到所述半导体层中，并进行第二退火处理以除去所述金属催化剂。 这里，p型杂质离子以6×10 3 / cm 2至5×10 15 / cm 2的剂量注入， / SUP>，并且吸除材料以1×10 11 / cm 2至3×10 15 / cm 2的剂量注入， / SUP>。

公开(公告)号：US07297980B2

公开(公告)日：2007-11-20

申请号：US10779781

申请日：2004-02-18

Applicant: Ji-Yong Park ,  Ul-Ho Lee ,  Jae-Bon Koo ,  Ki-Yong Lee ,  Hye-Hyang Park

Inventor： Ji-Yong Park ,  Ul-Ho Lee ,  Jae-Bon Koo ,  Ki-Yong Lee ,  Hye-Hyang Park

IPC: H01L29/04 ,  H01L29/786

CPC classification number: H01L29/78696 ,  G02F1/13454 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

Abstract: The present invention relates to a flat panel display device comprising a polycrystalline silicon thin film transistor and provides a flat panel display device having improved characteristics by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a driving circuit portion and active channel regions of pixel portion. This may be achieved by having a different number of grain boundaries included in the polycrystalline silicon thin film formed in active channel regions of a switching thin film transistor and a driving thin film transistor formed in the pixel portion, and by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a thin film transistor for driving the pixel portion for each red, green and blue of the pixel portion. Further, this may be achieved by having a different number of grain boundaries included in polycrystalline silicon formed in active channel regions of an NMOS thin film transistor and a PMOS thin film transistor for forming CMOS transistor used in flat panel display device, thereby constructing a thin film transistor to obtain the improved characteristics for each transistor.

Abstract translation: 本发明涉及一种包括多晶硅薄膜晶体管的平板显示装置，通过在驱动电路的有源沟道区域中形成的多晶硅薄膜中包含不同数量的晶界，提供具有改进特性的平板显示装置 像素部分和有源沟道区域。 这可以通过在形成在像素部分中的开关薄膜晶体管和驱动薄膜晶体管的有源沟道区域中形成的多晶硅薄膜中包含不同数量的晶界，并且通过具有不同数量的晶粒来实现 包括在形成在用于驱动像素部分的每个红，绿和蓝的像素部分的薄膜晶体管的有源沟道区域中的多晶硅薄膜中的边界。 此外，这可以通过在NMOS薄膜晶体管的有源沟道区域中形成的多晶硅中包含不同数量的晶界和用于形成用于平板显示器件的CMOS晶体管的PMOS薄膜晶体管来实现，从而构造薄的 以获得每个晶体管的改进特性。

公开(公告)号：US07220993B2

公开(公告)日：2007-05-22

申请号：US10990514

申请日：2004-11-18

Applicant: Hoon Kim ,  Jin-Wook Seo ,  Ki-Yong Lee

Inventor： Hoon Kim ,  Jin-Wook Seo ,  Ki-Yong Lee

IPC: H01L29/76

CPC classification number: H01L29/66757 ,  H01L27/1277 ,  H01L29/78675

Abstract: A thin film transistor and method for fabricating the same are provided. The thin film transistor comprises a semiconductor layer having a MILC region that has first crystalline grains crystallized by MILC method and second crystalline grains disposed between the first crystalline grains and having different crystalline properties from the first crystalline grains.

Abstract translation: 提供一种薄膜晶体管及其制造方法。 薄膜晶体管包括具有通过MILC方法结晶的第一晶粒的MILC区域和设置在第一晶粒之间并且具有与第一晶粒具有不同晶体性质的第二晶粒的半导体层。

公开(公告)号：US20050222245A1

公开(公告)日：2005-10-06

申请号：US10510923

申请日：2002-04-09

Applicant: Jeong-Seon Yoon ,  Ji-Young Lee ,  Young-Choong Kim ,  Ki-Yong Lee ,  Sang-Hyun Sung ,  Hak-Joong Kim ,  So-Young Kang

Inventor： Jeong-Seon Yoon ,  Ji-Young Lee ,  Young-Choong Kim ,  Ki-Yong Lee ,  Sang-Hyun Sung ,  Hak-Joong Kim ,  So-Young Kang

IPC: C07D493/04 ,  A61K31/366 ,  C07D493/02

CPC classification number: C07D493/04

Abstract: The present invention relates to compounds of the following formula (I) or pharmaceutically acceptable salts thereof. The present invention also relates to use for a cognitive-enhancing agent of compounds of the following formula (I) or pharmaceutically acceptable salts thereof and to a process for preparing the same. Further, the present invention relates to use for a congnitive-enhancing agent of decursin of the following formula (II) or pharmaceutically acceptable salts thereof. In addition, the present invention relates to extracts of Angelica gigantis Radix comprising decursin of the following formula (II), having cognitive-enhancing effects.

Abstract translation: 本发明涉及下式（I）的化合物或其药学上可接受的盐。 本发明还涉及下式（I）化合物或其药学上可接受的盐的认知增强剂及其制备方法的用途。 此外，本发明涉及下式（II）的前胡素的认知增强剂或其药学上可接受的盐的用途。 此外，本发明涉及包含具有认知增强作用的下式（II）的前胡素的当归提取物。

公开(公告)号：US20050105037A1

公开(公告)日：2005-05-19

申请号：US10959977

申请日：2004-10-08

Applicant: Hoon Kim ,  Ki-Yong Lee ,  Jin-Wook Seo

Inventor： Hoon Kim ,  Ki-Yong Lee ,  Jin-Wook Seo

IPC: G02F1/136 ,  G02F1/1345 ,  G02F1/1362 ,  G09F9/30 ,  G09G3/00 ,  G09G3/36 ,  H01L21/00 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/32

CPC classification number: G02F1/13624 ,  H01L27/1229 ,  H01L27/1277 ,  H01L27/1285 ,  H01L27/3244

Abstract: A flat panel display and method for fabricating the same are disclosed. In the flat panel display a substrate includes a pixel region having a plurality of unit pixels, and a peripheral circuit region arranged in the periphery of the pixel region. The peripheral circuit region also includes a driving circuit for driving the plurality of unit pixels. At least one circuit thin film transistor is positioned in the peripheral circuit region and includes a first semiconductor layer crystallized by a sequential lateral solidification method. At least one pixel thin film transistor is positioned in the pixel region and includes a second semiconductor layer having a channel region crystallized by one of a metal induced crystallization method or a metal induced lateral crystallization method.

Abstract translation: 公开了一种平板显示器及其制造方法。 在平板显示器中，基板包括具有多个单位像素的像素区域和布置在像素区域周边的外围电路区域。 外围电路区域还包括用于驱动多个单位像素的驱动电路。 至少一个电路薄膜晶体管位于外围电路区域中，并且包括通过顺序横向固化方法结晶的第一半导体层。 至少一个像素薄膜晶体管位于像素区域中，并且包括具有通过金属诱导结晶法或金属诱导横向结晶法中的一种结晶的沟道区的第二半导体层。

公开(公告)号：US06759679B2

公开(公告)日：2004-07-06

申请号：US10173977

申请日：2002-06-19

Applicant: Ki-Yong Lee

Inventor： Ki-Yong Lee

IPC: H01L2976

CPC classification number: H01L29/78696 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/78675

Abstract: A poly-silicon layer of a thin film transistor (TFT) having an active channel region, wherein a probability P that a maximum number of a primary grain boundary exists on the active channel region is not 0.5, the probability obtained by the following equation: P = D - ( N ⁢   ⁢ max - 1 ) · Gs Gs , where D=L cos &thgr;+W sin &thgr;, L is a channel length of the active channel region, W is a width of the active channel region, Nmax is the maximum number of the primary boundary existing on the active channel region, Gs is a grain size, and &thgr; is a tilt angle of the primary grain boundary and the display device having thereof.

Abstract translation: 具有有源沟道区域的薄膜晶体管（TFT）的多晶硅层，其中存在于有源沟道区上的一次晶界的最大数目的概率P不为0.5，通过下式计算得到的概率： 其中D = Lcosθ+ Wsinθ，L是有源信道区域的信道长度，W是有效信道区域的宽度，Nmax是存在于有源信道区域上的主边界的最大数目，Gs是 晶粒尺寸，θ是一次晶界的倾斜角和具有该晶粒的显示装置。

公开(公告)号：US06720578B2

公开(公告)日：2004-04-13

申请号：US10298571

申请日：2002-11-19

Applicant: Ki-Yong Lee

Inventor： Ki-Yong Lee

IPC: H01L2904

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/78645 ,  H01L29/78672 ,  H01L29/78696

Abstract: A polycrystalline silicon thin film for a TFT and a display device using the same where the number of crystal grain boundaries exerts a fatal influence on movement of electric charge carrier, providing a distance “S” between active channels of the TFT having dual or multiple channels with a relation S=mGs·sec &thgr;−L, and also providing a display device in which uniformity of TFT characteristics is improved by synchronizing the number of the crystal grain boundaries included in each of the channels of the dual or multiple channels S=mGs·sec &thgr;−L Gs is a size of crystal grains of the polycrystalline silicon thin film, m is an integer of 1 or more, &thgr; is an inclined angle where fatal crystal grain boundaries, that is, “primary” crystal grain boundaries are inclined in a direction perpendicular to an active channel direction, and L represents a length of active channels for each TFT having dual or multiple channels.

Abstract translation: 一种用于TFT的多晶硅薄膜和使用该多晶硅薄膜的显示装置，其中晶粒边界的数量对电荷载流子的移动造成致命的影响，在具有双通道或多通道的TFT的有源通道之间提供距离“S” 具有关系S =mGs.secθ-L，并且还提供一种显示装置，其中通过使包括在双通道或多通道中的每个通道中的晶粒边界的数量同步来提高TFT特性的均匀性.Gs是尺寸 的多晶硅薄膜的晶粒，m为1以上的整数，θ为致死晶界，即“初级”晶界在垂直于有源沟道方向的方向上倾斜的倾斜角 L表示具有双通道或多通道的每个TFT的有源通道的长度。

公开(公告)号：US09303313B2

公开(公告)日：2016-04-05

申请号：US13440638

申请日：2012-04-05

Applicant: Yun-Mo Chung ,  Ki-Yong Lee ,  Min-Jae Jeong

Inventor： Yun-Mo Chung ,  Ki-Yong Lee ,  Min-Jae Jeong

IPC: C23C14/24 ,  C23C14/35 ,  H01J37/34 ,  H01J37/32

CPC classification number: C23C14/352 ,  H01J37/32568 ,  H01J37/3417

Abstract: A separated target apparatus includes a base plate; and a plurality of source units including a plurality of separated targets that are adhered on one surface of the base plate and that form a regular array, and a plurality of magnets that are adhered on the other surface of the base plate and that make a pair with the plurality of separated targets. The plurality of source units are arrayed in parallel at an angle between a first direction that is a direction of the regular array and a second direction that is perpendicular to the first direction. Sputtering is performed by using the separated target apparatus having the aforementioned structure.

Abstract translation: 分离的目标装置包括基板; 以及多个源单元，其包括粘附在所述基板的一个表面上并形成规则阵列的多个分离的靶，以及多个磁体，所述多个磁体粘附在所述基板的另一个表面上并且成对 与多个分离的目标。 多个源单元以规则阵列的方向的第一方向和垂直于第一方向的第二方向之间的角度平行排列。 通过使用具有上述结构的分离的目标装置进行溅射。

公开(公告)号：US08841206B2

公开(公告)日：2014-09-23

申请号：US13211700

申请日：2011-08-17

Applicant: Byoung-Keon Park ,  Jong-Ryuk Park ,  Yun-Mo Chung ,  Tak-Young Lee ,  Jin-Wook Seo ,  Ki-Yong Lee ,  Min-Jae Jeong ,  Yong-Duck Son ,  Byung-Soo So ,  Seung-Kyu Park ,  Dong-Hyun Lee ,  Kil-Won Lee ,  Jae-Wan Jung

Inventor： Byoung-Keon Park ,  Jong-Ryuk Park ,  Yun-Mo Chung ,  Tak-Young Lee ,  Jin-Wook Seo ,  Ki-Yong Lee ,  Min-Jae Jeong ,  Yong-Duck Son ,  Byung-Soo So ,  Seung-Kyu Park ,  Dong-Hyun Lee ,  Kil-Won Lee ,  Jae-Wan Jung

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L27/32

CPC classification number: H01L27/3244 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1277 ,  H01L27/3262 ,  H01L29/1033 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78675 ,  H01L29/78678

Abstract: A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor.

Abstract translation: 形成多晶硅层的方法包括：形成第一非晶硅层并形成第二非晶硅层，使得第一非晶硅层和第二非晶硅层彼此具有不同的膜质量，并使第一非晶硅层 以及使用金属催化剂形成第一多晶硅层和第二多晶硅层的第二非晶硅层。 薄膜晶体管包括通过该方法形成的多晶硅层和包括薄膜晶体管的有机发光器件。