公开(公告)号：US06825496B2

公开(公告)日：2004-11-30

申请号：US10050597

申请日：2002-01-15

Applicant: Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

IPC: H01L2904

CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Abstract translation: 提供一种可以防止由于泄漏或其它原因引起的栅极电压变化并且同时可以防止开口率降低的发光器件。 电容器存储器由连接布线，绝缘膜和电容布线形成。 连接布线形成在栅电极和像素的TFT的有源层上，并与有源层连接。 绝缘膜形成在连接布线上。 电容布线形成在绝缘膜上。 这种结构使得电容器存储与TFT重叠，从而在保持开口率降低的同时增加电容器存储的容量。 因此，可以避免由于泄漏或其他原因导致的栅极电压的变化，以防止OLED的亮度变化和模拟驱动中屏幕的闪烁。

公开(公告)号：US06822263B2

公开(公告)日：2004-11-23

申请号：US10457928

申请日：2003-06-09

Applicant: Yoshinobu Satou ,  Katsuhisa Yuda ,  Hiroshi Tanabe

Inventor： Yoshinobu Satou ,  Katsuhisa Yuda ,  Hiroshi Tanabe

IPC: H01L2904

CPC classification number: H01L27/1296 ,  B23K26/04 ,  B23K26/066 ,  H01L21/02675 ,  H01L21/2026 ,  H01L23/544 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78633 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.

Abstract translation: 薄膜晶体管形成在透明基板上，具有栅极电极膜层和源极和漏极区域，并且还具有由与栅极中至少一个的构成材料相同的构成材料制成的对准标记 电极膜层和源极和漏极区，并且形成在与栅极电极膜层或源极和漏极区域相同的位置处。

公开(公告)号：US06809335B2

公开(公告)日：2004-10-26

申请号：US10431610

申请日：2003-05-08

Applicant: Woon-Yong Park

Inventor： Woon-Yong Park

IPC: H01L2904

CPC classification number: G02F1/136213 ,  G02F2001/136272 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

Abstract: A plurality of gate lines extending in a horizontal direction are formed on an insulating substrate, and a data line is formed perpendicular to the gate line thereby defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line is formed in the horizontal direction, and a storage electrode connected to the storage electrode line and forming a storage capacitance by overlapping the pixel electrode is formed in the pixel. A redundant repair line both ends of which overlap the storage wire of the neighboring pixel, and a storage wire connection line connecting the storage wires of a neighboring pixel are formed. In this structure, because the storage wires of a neighboring pixel are connected to each other through the storage wire connection line, the variation of the voltage for the storage capacitance may be minimized, and this results in a reduction of its distortion, such that crosstalk and flicker problems are minimized.

Abstract translation: 在绝缘基板上形成沿水平方向延伸的多个栅极线，并且垂直于栅极线形成数据线，由此限定矩阵阵列的像素。 通过数据线接收图像信号的像素电极形成在像素中，并且形成具有连接到栅极线的栅电极，连接到数据线的源电极和连接到像素电极的漏电极的薄膜晶体管 在栅极线和数据线相交的部分。 在水平方向上形成包括存储电极线的存储线，并且在像素中形成通过与像素电极重叠而与存储电极线连接并形成存储电容的存储电极。 冗余修复线的两端与相邻像素的存储线重叠，形成连接相邻像素的存储线的存储线连接线。 在该结构中，由于相邻像素的存储线通过存储线连接线彼此连接，所以可以使存储电容的电压的变化最小化，并且这导致其失真的减小，使得串扰 并且闪烁问题被最小化。

公开(公告)号：US06806496B2

公开(公告)日：2004-10-19

申请号：US09999163

申请日：2001-11-30

Applicant: Satoshi Inoue

Inventor： Satoshi Inoue

IPC: H01L2904

CPC classification number: H01L27/12 ,  H01L51/0541 ,  H01L51/0545

Abstract: In a manufacturing method in which a source line is provided around a pixel electrode provided on a substrate, an insulating film having open regions that will provide a source and a gate is formed, the source and the drain are formed, and a semiconductor film and a gate are provided on the source and drain, the above constituents are formed substantially under atmospheric pressure. Since manufacture can be accomplished substantially under the atmospheric pressure, no special apparatus, such as a vacuum chamber, is required, permitting a display device to be manufactured at lower cost.

公开(公告)号：US06806495B1

公开(公告)日：2004-10-19

申请号：US09566730

申请日：2000-05-09

Applicant: Shunpei Yamazaki ,  Jun Koyama ,  Setsuo Nakajima

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Setsuo Nakajima

IPC: H01L2904

CPC classification number: H01L27/1288 ,  G02F2001/136231 ,  H01L27/1214

Abstract: A liquid crystal display device; in the prior art has been high in its manufactural cost for the reason that TFTs have been fabricated using, at least, five photo-masks.

Abstract translation: 液晶显示装置; 在现有技术中，由于至少使用了5个光掩膜来制造TFT，所以其制造成本很高。

公开(公告)号：US06803601B2

公开(公告)日：2004-10-12

申请号：US10140424

申请日：2002-05-06

Applicant: Setsuo Nakajima

Inventor： Setsuo Nakajima

IPC: H01L2904

CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

Abstract: An object of the present invention is to provide a TFT of new structure in which the gate electrode overlaps with the LDD region and a TFT of such structure in which the gate electrode does not overlap with the LDD region. The TFT is made from crystalline semiconductor film and is highly reliable. The TFT of crystalline semiconductor film has the gate electrode formed from a first gate electrode 113 and a second gate electrode in close contact with said first gate electrode and gate insulating film. The LDD is formed by ion doping using said first gate electrode as a mask, and the source-drain region is formed using said second gate electrode as a mask. After that the second gate electrode in the desired region is selectively removed. In this way it is possible to form LDD region which overlaps with the second gate electrode.

Abstract translation: 本发明的目的是提供一种其中栅电极与LDD区重叠的新结构的TFT和其中栅电极不与LDD区重叠的结构的TFT。 TFT由结晶半导体膜制成，高度可靠。晶体半导体膜的TFT具有由第一栅电极113和与所述第一栅电极和栅极绝缘膜紧密接触的第二栅极形成的栅电极。 通过使用所述第一栅电极作为掩模的离子掺杂形成LDD，并且使用所述第二栅电极作为掩模形成源极 - 漏极区。 之后，选择性地去除所需区域中的第二栅电极。 以这种方式，可以形成与第二栅电极重叠的LDD区域。

公开(公告)号：US06803600B2

公开(公告)日：2004-10-12

申请号：US09983523

申请日：2001-10-24

Applicant: Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang

Inventor： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang

IPC: H01L2904

CPC classification number: H01L27/127 ,  G02F1/13454 ,  G02F2001/136245 ,  H01L21/76897 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78651 ,  H01L29/78666 ,  H01L29/78675

Abstract: An LDD structure is manufactured to have a desired aspect ratio of the height to the width of a gate electrode. The gate electrode is first deposited on a semiconductor substrate followed by ion implantation with the gate electrode as a mask to form a pair of impurity regions. The gate electrode is then anodic oxidized to form an oxide film enclosing the electrode. With the oxide film as a mask, highly doped regions are formed by ion implantation in order to define lightly doped regions between the highly doped regions and the channel region located therebetween.

Abstract translation: 制造LDD结构以具有期望的高度与栅电极的宽度的纵横比。 首先将栅电极沉积在半导体衬底上，随后以栅电极作为掩模进行离子注入，以形成一对杂质区。 然后对栅电极进行阳极氧化，形成包围电极的氧化膜。 以氧化物膜为掩模，通过离子注入形成高度掺杂的区域，以便在高掺杂区域和位于它们之间的沟道区域之间限定轻掺杂区域。

公开(公告)号：US06800873B2

公开(公告)日：2004-10-05

申请号：US10307966

申请日：2002-12-03

Applicant: Hongyong Zhang

Inventor： Hongyong Zhang

IPC: H01L2904

CPC classification number: G02F1/136227 ,  H01L27/124 ,  H01L29/66757 ,  H01L29/78633

Abstract: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can be made stable.

Abstract translation: 薄膜晶体管的沟道形成区域被从源极线延伸的电极和布线覆盖。 结果，防止了从薄膜晶体管上方的光照射沟道形成区域，从而可以使薄膜晶体管的特性稳定。

公开(公告)号：US06800872B2

公开(公告)日：2004-10-05

申请号：US10235493

申请日：2002-09-06

Applicant: Hiroaki Tanaka ,  Hiroyuki Uchida

Inventor： Hiroaki Tanaka ,  Hiroyuki Uchida

IPC: H01L2904

CPC classification number: H01L29/41733 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78633

Abstract: As a configuration of a gate island consisting of a laminated structure including a gate electrode, a gate insulating film and a semiconductor film for constituting a thin film transistor, the gate insulating film and the semiconductor film are formed into a plane shape equal to or smaller than the gate electrode and covered with a channel protection film. Further, a drain electrode and a source electrode are formed to be connected with the semiconductor film through openings provided to the channel protection film. Consequently, side surfaces of the semiconductor film and the gate insulating film can be covered with the channel protection film formed in an upper layer, and impurities existing in a liquid crystal layer can be prevented from entering the semiconductor film by diffusion or an electric field, thereby improving the characteristic of a TFT.

Abstract translation: 作为由包括栅电极，栅极绝缘膜和用于构成薄膜晶体管的半导体膜的层叠结构构成的栅极岛的结构，栅极绝缘膜和半导体膜形成为等于或小于 比栅电极和通道保护膜覆盖。 此外，漏电极和源极电极通过设置在通道保护膜上的开口与半导体膜连接。 因此，半导体膜和栅极绝缘膜的侧表面可以被形成在上层中的沟道保护膜覆盖，并且可以防止存在于液晶层中的杂质通过扩散或电场进入半导体膜， 从而提高TFT的特性。

公开(公告)号：US06787809B2

公开(公告)日：2004-09-07

申请号：US10644917

申请日：2003-08-21

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L2904

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Abstract translation: 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。