公开(公告)号：US07078255B2

公开(公告)日：2006-07-18

申请号：US10933545

申请日：2004-09-03

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L21/00 ,  H01L21/84

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

公开(公告)号：US07504290B2

公开(公告)日：2009-03-17

申请号：US11750630

申请日：2007-05-18

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L21/84

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Abstract translation: 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US20050023534A1

公开(公告)日：2005-02-03

申请号：US10933545

申请日：2004-09-03

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: G09F9/30 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/417 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Abstract translation: 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US06787809B2

公开(公告)日：2004-09-07

申请号：US10644917

申请日：2003-08-21

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L2904

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Abstract translation: 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US06642074B2

公开(公告)日：2003-11-04

申请号：US10172982

申请日：2002-06-18

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L2100

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Abstract translation: 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US20060228821A1

公开(公告)日：2006-10-12

申请号：US11451686

申请日：2006-06-13

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L21/00 ,  H01L21/84

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

公开(公告)号：US06429057B1

公开(公告)日：2002-08-06

申请号：US09410760

申请日：1999-10-01

Applicant: Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

Inventor： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC: H01L2100

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Abstract translation: 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US07507994B2

公开(公告)日：2009-03-24

申请号：US11625694

申请日：2007-01-22

Applicant: Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Doug-Gyu Kim

Inventor： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Doug-Gyu Kim

IPC: H01L29/04

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

Abstract translation: 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

公开(公告)号：US20070126005A1

公开(公告)日：2007-06-07

申请号：US11625694

申请日：2007-01-22

Applicant: Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Doug-Gyu Kim

Inventor： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Doug-Gyu Kim

IPC: H01L29/04

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

Abstract translation: 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

公开(公告)号：US20050170592A1

公开(公告)日：2005-08-04

申请号：US11080612

申请日：2005-03-16

Applicant: Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

Inventor： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC: G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L31/0376

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

Abstract translation: 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。