公开(公告)号：US08441835B2

公开(公告)日：2013-05-14

申请号：US12814410

申请日：2010-06-11

申请人： Sung Hyun Jo ,  Hagop Nazarian ,  Wei Lu

发明人： Sung Hyun Jo ,  Hagop Nazarian ,  Wei Lu

IPC分类号： G11C11/00

CPC分类号： H01L45/1608 ,  G11C13/0002 ,  G11C2213/33 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/148

摘要： A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

公开(公告)号：US08411485B2

公开(公告)日：2013-04-02

申请号：US12815318

申请日：2010-06-14

申请人： Hagop Nazarian ,  Sung Hyun Jo

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C14/0045 ,  G11C2213/33 ,  G11C2213/53 ,  H01L29/7881 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148

摘要： A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.

公开(公告)号：US20120320660A1

公开(公告)日：2012-12-20

申请号：US13592224

申请日：2012-08-22

申请人： Hagop NAZARIAN ,  Sung Hyun Jo

发明人： Hagop NAZARIAN ,  Sung Hyun Jo

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/15 ,  G11C2213/33

摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

摘要翻译： 一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

公开(公告)号：US08320160B2

公开(公告)日：2012-11-27

申请号：US13051296

申请日：2011-03-18

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C11/40

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C16/0483 ,  G11C2213/33 ,  G11C2213/53 ,  G11C2213/56 ,  G11C2213/75

摘要： A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells.

摘要翻译： 非易失性存储器件包括第一选择晶体管，第二选择晶体管和设置在第一和第二选择晶体管之间的第一存储单元串。 每个第一存储单元具有第一电阻存储单元和第一晶体管。 第一电阻存储单元与第一晶体管的栅极串联。 非易失性存储器件还包括耦合到第一选择晶体管的漏极和多个字线的第一位线。 每个字线耦合到第一存储器单元之一。

公开(公告)号：US08279674B2

公开(公告)日：2012-10-02

申请号：US12824352

申请日：2010-06-28

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20120074507A1

公开(公告)日：2012-03-29

申请号：US12894057

申请日：2010-09-29

申请人： Sung Hyun JO ,  Hagop Nazarian

发明人： Sung Hyun JO ,  Hagop Nazarian

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

摘要： An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device.

摘要翻译： 集成电路器件。 集成电路器件包括具有表面区域的半导体衬底。 栅极电介质层覆盖在衬底的表面区域上。 该器件包括具有p +有源区的MOS器件。 p +有源区形成用于电阻式开关器件的第一电极。 电阻开关器件包括覆盖p +有源区的非晶硅开关材料和覆盖在第一金属导体结构上的金属电极。 金属电极包括金属材料，当对金属电极施加正偏压时，在非晶硅开关材料中形成金属区域。 MOS器件为集成电路器件提供选择晶体管。

公开(公告)号：US20110122708A1

公开(公告)日：2011-05-26

申请号：US12346699

申请日：2008-12-30

申请人： Hagop NAZARIAN ,  Imran KHAN ,  Chieu-Yin CHIA

发明人： Hagop NAZARIAN ,  Imran KHAN ,  Chieu-Yin CHIA

IPC分类号： G11C16/06

CPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/3454

摘要： A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.

摘要翻译： 提供半导体存储器件和用于在半导体存储器件中执行存储器操作的方法。 半导体存储器件包括多个预定存储器阵列，位线解码器和控制器。 控制器向位线解码器提供存储器操作信号，并且在对多个预定存储器阵列的位线进行预充电之后，根据存储器操作对多个预定存储器阵列中的一个或多个中的选定存储单元执行存储器操作 信号。 位线解码器包括多个扇区选择晶体管，并且响应于存储器操作信号确定多个预定存储器阵列中的选定的行以及多个预定存储器阵列中的选定行中的选定行和未选择的行。 位线解码器还将多个预定存储器阵列的位线预先充电到第一电压电位，然后关闭多个预定存储器阵列中未选择的存储器阵列的扇区选择晶体管和多个预定存储器中的所选择的存储器的未选择的行 阵列，同时在所述控制器执行所述存储器操作之前，将所述多个预定存储器阵列中的选定行的选定行的扇区选择晶体管保持在所述第一电压电位。

公开(公告)号：US07567457B2

公开(公告)日：2009-07-28

申请号：US11929724

申请日：2007-10-30

申请人： Hagop Nazarian ,  Harry Kuo ,  Michael Achter

发明人： Hagop Nazarian ,  Harry Kuo ,  Michael Achter

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C8/14 ,  G11C8/08 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/10

摘要： An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.

摘要翻译： 一种包括多对非易失性存储器（“NVM”）单元的二维或三维阵列的装置，其被耦合以使能NVM单元的编程和擦除。 多对NVM单元电连接到字线和位线。 每对NVM单元包括第一存储单元和第二存储单元。 第一和第二存储单元包括第一源极/漏极，第二源极/漏极和控制栅极。 第一存储单元的第一源极/漏极连接到位线之一。 第一存储单元的第二源极/漏极连接到第二存储单元的第一源极/漏极。 第二存储单元的第二源极/漏极连接到另一个位线。 第一和第二存储单元的控制栅极连接到不同的字线。

公开(公告)号：US20090113115A1

公开(公告)日：2009-04-30

申请号：US11928865

申请日：2007-10-30

申请人： Hagop Nazarian ,  Ali Pourkeramati

发明人： Hagop Nazarian ,  Ali Pourkeramati

IPC分类号： G06F12/02 ,  G06F12/06

CPC分类号： G11C11/5621 ,  G11C16/08 ,  G11C2211/5641

摘要： A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.

摘要翻译： 公开了一种存储器件，并且包括存储器单元阵列和配置成以单级单元模式寻址阵列的第一部分的分区系统，以及以多级单元模式的阵列的第二部分。

公开(公告)号：US20070279033A1

公开(公告)日：2007-12-06

申请号：US11891078

申请日：2007-08-09

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G05F3/16

CPC分类号： G05F3/205 ,  Y10S323/901

摘要： An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its operation in its desired stable state. Once the self-bias circuit converges to its desired state of operation a start-up voltage reference/voltage clamping circuit shuts off current flow to the self-bias circuit and the start-up circuit enters a low power mode of operation to reduce its overall current and power draw. This allows for embodiments of the present invention to be utilized in portable and/or low power devices where low power consumption is of increased importance. In one embodiment of the present invention, a band-gap voltage reference circuit is initiated utilizing a start-up circuit.

摘要翻译： 描述了用于自偏置电路的改进的启动电路和方法，其将启动电压和电流施加到自偏置电路以将其操作初始化为其所需的稳定状态。 一旦自偏置电路收敛到其期望的操作状态，启动电压基准/电压钳位电路就切断到自偏压电路的电流，并且启动电路进入低功率运行模式以减小其整体 电流和功率消耗。 这允许将本发明的实施例用于低功耗增加重要性的便携式和/或低功率设备中。 在本发明的一个实施例中，利用启动电路启动带隙电压参考电路。