公开(公告)号：US10474173B2

公开(公告)日：2019-11-12

申请号：US16057435

申请日：2018-08-07

申请人： ABLIC Inc.

发明人： Shingo Nakashima

IPC分类号： G05F1/575 ,  G05F1/56

摘要： A voltage regulator is equipped with the first and the second source-grounded amplifier circuits connected to an output terminal of a differential amplifier circuit; a phase compensation circuit having a resistor part and a capacitor part, and connected between an output terminal of the first source-grounded amplifier circuit and an output terminal of the second source-grounded amplifier circuit; and an output transistor connected to the output terminal of the second source-grounded amplifier circuit. At least one of the resistor part and the capacitor part of the phase compensation circuit has a filter.

公开(公告)号：US20190333888A1

公开(公告)日：2019-10-31

申请号：US16507308

申请日：2019-07-10

申请人： ABLIC Inc.

发明人： Noriyuki KIMURA

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/288 ,  H01L21/78 ,  H01L21/56 ,  H01L21/3105 ,  H01L29/417 ,  H01L21/683

摘要： A resin-encapsulated semiconductor device includes a bump electrode formed on an element surface side of a semiconductor chip, a conductive layer electrically connected to the bump electrode, and a resin encapsulation body covering the semiconductor chip, the bump electrode, and the conductive layer. On a back surface of the semiconductor chip that is flush with a back surface of the resin encapsulation body, a metal layer and a laminated film are formed. The laminated film is formed on a front surface of the conductive layer, and an external terminal is arranged on an inner side of an outer edge of the semiconductor chip.

公开(公告)号：US20190318997A1

公开(公告)日：2019-10-17

申请号：US16377589

申请日：2019-04-08

申请人： ABLIC Inc.

发明人： Kohei KAWABATA ,  Masahiro HATAKENAKA

IPC分类号： H01L23/00 ,  H01L29/06 ,  H01L23/58 ,  H01L23/552 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213

摘要： Provided is a semiconductor device capable of shielding X-rays irradiated from a side surface side of a semiconductor substrate and a method of manufacturing the same. The semiconductor device includes: gate insulating film; a gate electrode; a source/drain region; an element isolation region; a guard ring surrounding the element isolation region; an interlayer insulating film; a contact trench in the interlayer insulating film; a barrier metal film for shielding X-rays covering inner side surfaces and a bottom surface of the contact trench; and a metal film connected to the guard ring.

公开(公告)号：US20190305686A1

公开(公告)日：2019-10-03

申请号：US16363061

申请日：2019-03-25

申请人： ABLIC Inc.

发明人： Kotaro WATANABE

IPC分类号： H02M3/158 ,  H02M3/157

摘要： Provided is a power supply circuit including a series regulator step-down power circuit, a charge pump step-up power circuit, and a voltage selection circuit to which a voltage of an input terminal and a voltage of an output terminal are supplied and configured to output a higher voltage from the supplied voltages. A connection point of a first resistor and a second resistor which are connected between the output terminal and a ground terminal is connected to an input of a differential amplifier circuit. An output of the differential amplifier circuit is connected to a gate terminal of an output transistor via a first switch. An output of the voltage selection circuit is connected to the gate terminal of the output transistor via a second switch. The output of the voltage selection circuit is connected to a substrate electrode of the output transistor.

公开(公告)号：US10401891B2

公开(公告)日：2019-09-03

申请号：US16227740

申请日：2018-12-20

申请人： ABLIC Inc.

发明人： Kaoru Sakaguchi

IPC分类号： G05F3/24 ,  G05F3/26 ,  H01L27/06 ,  H01L27/088

摘要： A reference voltage circuit includes: a depletion type MOS transistor and an enhancement type MOS transistor connected in series, and having gates thereof connected in common, the enhancement type MOS transistor providing a reference voltage from a drain thereof, the depletion type MOS transistor including at least a first depletion type MOS transistor and a second depletion type MOS transistor connected in series; and a capacitor having one end connected to a drain of the first depletion type MOS transistor, and the other end connected to a source of the first depletion type MOS transistor.

公开(公告)号：US20190220048A1

公开(公告)日：2019-07-18

申请号：US16221770

申请日：2018-12-17

申请人： ABLIC Inc.

发明人： Tsutomu TOMIOKA

IPC分类号： G05F1/571 ,  G01R19/165 ,  H03K17/687

CPC分类号： G05F1/571 ,  G01R19/16528 ,  H02H7/1213 ,  H03K17/6871

摘要： A reverse-current-prevention circuit includes a reverse-current-prevention transistor of a P-channel MOS transistor inserted between an input terminal supplied with a power supply voltage and an output stage transistor of a P-channel MOS transistor providing an output voltage from an output terminal, and a reverse-current-prevention controller configured to turn the reverse-current-prevention transistor from on to off according to exceedance of the output voltage to the power supply voltage. The reverse-current-prevention controller includes a first transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to the output terminal and the input terminal, and a second transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to a drain of the first transistor and a gate of the reverse-current-prevention transistor, and a drain grounded.

公开(公告)号：US10354968B2

公开(公告)日：2019-07-16

申请号：US15926830

申请日：2018-03-20

申请人： ABLIC Inc.

发明人： Noriyuki Kimura

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L29/417 ,  H01L21/288 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/31

摘要： The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3) electrically connected to the bump electrode (2), and a resin encapsulation body (6) covering the semiconductor chip (1), the bump electrode (2), and the conductive layer (3). On a back surface of the semiconductor chip (1) that is flush with a back surface of the resin encapsulation body (6), a metal layer (4) and a laminated film (5) are formed. The laminated film (5) is formed on a front surface of the conductive layer (3). The external terminal (9) is arranged on an inner side of an outer edge of the semiconductor chip (1).

公开(公告)号：US20190187739A1

公开(公告)日：2019-06-20

申请号：US16220762

申请日：2018-12-14

申请人： ABLIC Inc.

发明人： Masakazu SUGIURA ,  Atsushi IGARASHI ,  Nao OTSUKA

IPC分类号： G05F3/26 ,  G05F3/24 ,  G05F3/30

CPC分类号： G05F3/262 ,  G05F3/24 ,  G05F3/30

摘要： A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.

公开(公告)号：US10263076B2

公开(公告)日：2019-04-16

申请号：US15874342

申请日：2018-01-18

申请人： ABLIC Inc.

发明人： Mitsuhiro Yoshimura ,  Masahiro Hatakenaka

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739

摘要： To obtain a semiconductor device in which a reduction in channel formation density in a trench extending direction is suppressed, provided is a semiconductor device including a first region and a second region alternately arranged in the trench extending direction. The first region includes a first front surface semiconductor electrode layer of a first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor device to the first height to which a gate electrode is embedded into the trench. The second region includes a base contact region having a depth from the front surface of the semiconductor device to the second height higher than the first height and a second front surface semiconductor electrode layer of the first conductivity type from the first height to the second height.

公开(公告)号：US10262924B2

公开(公告)日：2019-04-16

申请号：US15936738

申请日：2018-03-27

申请人： ABLIC Inc.

发明人： Kiyoaki Kadoi

IPC分类号： H01L23/48 ,  H01L23/49 ,  H01L23/00 ,  H01L23/482 ,  H01L23/055 ,  H01L23/495 ,  H05K3/00

摘要： Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.