公开(公告)号：US20190318997A1

公开(公告)日：2019-10-17

申请号：US16377589

申请日：2019-04-08

申请人： ABLIC Inc.

发明人： Kohei KAWABATA ,  Masahiro HATAKENAKA

IPC分类号： H01L23/00 ,  H01L29/06 ,  H01L23/58 ,  H01L23/552 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213

摘要： Provided is a semiconductor device capable of shielding X-rays irradiated from a side surface side of a semiconductor substrate and a method of manufacturing the same. The semiconductor device includes: gate insulating film; a gate electrode; a source/drain region; an element isolation region; a guard ring surrounding the element isolation region; an interlayer insulating film; a contact trench in the interlayer insulating film; a barrier metal film for shielding X-rays covering inner side surfaces and a bottom surface of the contact trench; and a metal film connected to the guard ring.

公开(公告)号：US20210305425A1

公开(公告)日：2021-09-30

申请号：US17209200

申请日：2021-03-22

申请人： ABLIC Inc.

发明人： Masahiro HATAKENAKA

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L29/66

摘要： In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.

公开(公告)号：US20180284833A1

公开(公告)日：2018-10-04

申请号：US15940010

申请日：2018-03-29

申请人： ABLIC Inc.

发明人： Hideo YOSHINO ,  Masahiro HATAKENAKA

IPC分类号： G05F3/26

CPC分类号： G05F3/262

摘要： A reference voltage generator is constructed to be equipped with a first constant current circuit which outputs a first constant current with respect to an input voltage, a second constant current circuit which outputs a second constant current, and a voltage generation circuit which generates a voltage based on an input current, and to take a current based on the first constant current and the second constant current as an input current of the voltage generation circuit and output a reference voltage from the voltage generation circuit.

公开(公告)号：US20180286975A1

公开(公告)日：2018-10-04

申请号：US15938176

申请日：2018-03-28

申请人： ABLIC Inc.

发明人： Masahiro HATAKENAKA ,  Mitsuhiro YOSHIMURA

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66

摘要： A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.

公开(公告)号：US20180286970A1

公开(公告)日：2018-10-04

申请号：US15936723

申请日：2018-03-27

申请人： ABLIC Inc.

发明人： Mitsuhiro YOSHIMURA ,  Masahiro HATAKENAKA

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/78

摘要： A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a base region formed in the semiconductor substrate; a trench formed from the first surface and the second surface into the semiconductor substrate; a gate insulating film covering an inner side of the trench; a gate electrode embedded to a third height; an insulating film formed on the gate electrode; a first region which has the first surface and in which a base contact region is formed; and a second region which has the second surface and in which a source region is formed, the first region and the second region being alternately arranged in the trench extension direction to prevent a reduction in channel formation density.

公开(公告)号：US20180269287A1

公开(公告)日：2018-09-20

申请号：US15874342

申请日：2018-01-18

申请人： ABLIC Inc.

发明人： Mitsuhiro YOSHIMURA ,  Masahiro HATAKENAKA

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： To obtain a semiconductor device in which a reduction in channel formation density in a trench extending direction is suppressed, provided is a semiconductor device including a first region and a second region alternately arranged in the trench extending direction. The first region includes a first front surface semiconductor electrode layer of a first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor device to the first height to which a gate electrode is embedded into the trench. The second region includes a base contact region having a depth from the front surface of the semiconductor device to the second height higher than the first height and a second front surface semiconductor electrode layer of the first conductivity type from the first height to the second height.