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    Semiconductor device manufacturing method and semiconductor device
    61.
    发明授权
    Semiconductor device manufacturing method and semiconductor device 失效
    半导体器件制造方法和半导体器件

    公开(公告)号：US07763926B2

    公开(公告)日：2010-07-27

    申请号：US12246533

    申请日：2008-10-07

    Applicant: Masahiko Takeuchi

    Inventor： Masahiko Takeuchi

    IPC: H01L27/108

    CPC classification number: H01L28/65 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/105 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

    Abstract translation: 即使在形成电容器的电介质膜时进行氧化，也能够实现存储元件的接触电阻的降低和逻辑元件的接触电阻的降低的技术。 导电阻挡层（82）设置在电连接到源极/漏极区域（59）的接触插塞（83b）的顶端。 电容器（73）的下电极（70）形成为与接触塞（83b）的导电阻挡层（82）接触，然后电容器（73）的电介质膜（71）和上电极（72）依次 形成。 在逻辑区域中，接触插塞（25）形成在上层中，使得它们分别与电源/漏极区域（9）电连接的接触插塞（33）接触。

    LED DRIVING CIRCUIT, SEMICONDUCTOR ELEMENT AND IMAGE DISPLAY DEVICE
    63.
    发明申请
    LED DRIVING CIRCUIT, SEMICONDUCTOR ELEMENT AND IMAGE DISPLAY DEVICE 审中-公开
    LED驱动电路，半导体元件和图像显示器件

    公开(公告)号：US20100177127A1

    公开(公告)日：2010-07-15

    申请号：US12683697

    申请日：2010-01-07

    Applicant: Noboru AKIYAMA ,  Takayuki HASHIMOTO ,  Takashi HIRAO ,  Nobuyoshi MATSUURA

    Inventor： Noboru AKIYAMA ,  Takayuki HASHIMOTO ,  Takashi HIRAO ,  Nobuyoshi MATSUURA

    IPC: G06F3/038 ,  G09G5/10

    CPC classification number: G09G3/36

    Abstract: An LED driving circuit driving an LED array includes: n constant-current driving elements having a vertical structure, each of which is connected to each of LED strings in series and drives the LED string with a constant current; n constant-current control circuits controlling on voltages of the constant-current driving elements so that currents flowing to the LED strings become constant currents; a lowest-voltage detecting circuit to which terminal voltages of the constant-current driving elements on an LED string side are inputted, the lowest-voltage detecting circuit selecting a lowest voltage from among the terminal voltages and outputting a command signal based on difference between the lowest voltage and a predetermined set voltage; and a power-supply control circuit controlling a voltage applied to the LED array to a voltage lower than an initial set voltage based on the command signal.

    Abstract translation: 驱动LED阵列的LED驱动电路包括：具有垂直结构的n个恒定电流驱动元件，其各自串联连接到每个LED串，并以恒定电流驱动LED串; n个恒流控制电路，控制恒流驱动元件的电压，使流到LED串的电流成为恒定电流; 输入LED串侧的恒流驱动元件的端子电压的最低电压检测电路，所述最低电压检测电路从所述端子电压中选择最低电压，并基于所述第二电压检测电路 最低电压和预定的设定电压; 以及电源控制电路，其基于所述命令信号，将施加到所述LED阵列的电压控制为低于初始设定电压的电压。

    SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF
    65.
    发明申请
    SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF 有权
    具有线的半导体器件及其制造方法

    公开(公告)号：US20100176511A1

    公开(公告)日：2010-07-15

    申请号：US12730039

    申请日：2010-03-23

    Applicant: Kazuyoshi Maekawa ,  Kenichi Mori

    Inventor： Kazuyoshi Maekawa ,  Kenichi Mori

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/76862 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

    Abstract translation: 半导体器件包括层间绝缘膜，设置在层间绝缘膜中的底层线，覆盖层间绝缘膜的衬里膜，覆盖衬垫膜的层间绝缘膜。 底线具有较低的孔，衬里膜和层间绝缘膜具有与下孔连通的上孔，下孔的直径大于上孔。 半导体器件还包括设置在下孔内壁表面的导电膜，沿着上孔的内壁表面设置的阻挡金属和填充上孔和下孔的Cu膜。 导电膜含有与阻挡金属物质相同的物质。 因此可以获得高可靠性的半导体器件。

    Semiconductor integrated circuit
    66.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07755148B2

    公开(公告)日：2010-07-13

    申请号：US12429024

    申请日：2009-04-23

    Applicant: Yusuke Kanno ,  Kenichi Yoshizumi

    Inventor： Yusuke Kanno ,  Kenichi Yoshizumi

    IPC: H01L27/00

    CPC classification number: H03K19/0016 ,  H01L27/0207 ,  H01L27/11807

    Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.

    Abstract translation: 逻辑LSI包括第一电源域PD1至PD4，厚膜电源开关SW1至SW4，以及电源开关控制器PSWC1至PSWC4。 厚膜功率开关由在外部输入/输出电路I / O公用的工艺中制造的厚膜功率晶体管形成。 第一电源域包括经由虚拟接地线VSSM1至VSSM4连接到厚膜电源开关的包括逻辑块的第二电源域SPD11至SPD42，控制电路块SCB1至SCB4和薄膜电源开关SWN11至SWN42，以及 由在逻辑块公用的工艺中制造的薄膜功率晶体管形成。 以这种方式，具有彼此不同的栅绝缘膜厚度的电源开关被垂直堆叠以便处于分层结构，并且每个电源开关由对应于每个模式的电源开关控制器和控制电路块分别控制。

    Semiconductor nonvolatile memory device
    68.
    发明授权
    Semiconductor nonvolatile memory device 有权
    半导体非易失性存储器件

    公开(公告)号：US07751255B2

    公开(公告)日：2010-07-06

    申请号：US12233670

    申请日：2008-09-19

    Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

    Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

    Semiconductor device and a method of manufacturing the same
    69.
    发明授权
    Semiconductor device and a method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07750427B2

    公开(公告)日：2010-07-06

    申请号：US12349348

    申请日：2009-01-06

    Applicant: Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

    Inventor： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

    IPC: H01L27/095

    CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/7833

    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSi2 layer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.

    Abstract translation: 提供了一种技术，其中可以在同一芯片中形成高性能肖特基势垒二极管和其他半导体元件，以控制步骤数量的增加。 在氧化硅膜沉积在其上形成n沟道型MISFET的衬底上并且选择性地去除栅电极和n +型半导体区上的氧化硅膜之后，在衬底上沉积Co膜，并且CoSi 2层是 通过对基板进行热处理而形成在n +型半导体区域和栅电极之上。 在氮化硅膜沉积在衬底上之后，通过去除肖特基势垒二极管的阳极形成部分处的氮化硅膜和氧化硅膜来形成到达衬底的孔径，在衬底上沉积Ti膜 在孔的内侧，通过对基板进行热处理，在孔的底部形成成为肖特基势垒二极管的阳极的TiSi 2层。

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