Invention Application
- Patent Title: SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSES WITH LESS POWER CONSUMPTION AND INTERCONNECTION ARRANGEMENT
- Patent Title (中): 具有低功耗和互连布置的电熔丝的半导体器件
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Application No.: US12723218Application Date: 2010-03-12
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Publication No.: US20100165775A1Publication Date: 2010-07-01
- Inventor: Shigeki OBAYASHI , Toshiaki Yonezu , Tokeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
- Applicant: Shigeki OBAYASHI , Toshiaki Yonezu , Tokeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Priority: JP2006-145759(P) 20060525
- Main IPC: G11C17/18
- IPC: G11C17/18 ; H01L23/525
Abstract:
In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.
Public/Granted literature
- US08331185B2 Semiconductor device having electrical fuses with less power consumption and interconnection arrangement Public/Granted day:2012-12-11
Information query
