公开(公告)号：US20230343372A1

公开(公告)日：2023-10-26

申请号：US17725564

申请日：2022-04-21

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H03K19/017

CPC classification number: G11C7/1039 ,  G11C7/1096 ,  G11C7/1069 ,  G11C7/12 ,  G11C8/08 ,  H03K19/01742

Abstract: An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.

公开(公告)号：US20230299773A1

公开(公告)日：2023-09-21

申请号：US17697856

申请日：2022-03-17

Applicant: QuickLogic Corporation

Inventor： Ket Chong YAP ,  Chihhung Liao

IPC: H03K19/1776 ,  G11C11/419 ,  H03K19/20

CPC classification number: H03K19/1776 ,  G11C11/419 ,  H03K19/20

Abstract: An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.

公开(公告)号：US10775206B2

公开(公告)日：2020-09-15

申请号：US15163474

申请日：2016-05-24

Applicant: QuickLogic Corporation

Inventor： Rajasekaran Ramasubramanian ,  Dung Le

IPC: G01D9/32 ,  H03M7/30 ,  H04L9/32 ,  G06F9/46 ,  G01D21/02 ,  G01D9/00

Abstract: A sensor hub includes a bit packer that receives sensor data from a plurality of sensors and bit packs the sensor data so that the sensor ID, time stamp and each axis of the measured data is stored contiguously. The bit packer may compress the sensor data by removing the sensor ID and/or the time stamp in the sensor data. The bit packed sensor data is stored in batching memory. A bit unpacker receives the sensor data from the batching memory and unpacks the sensor data, e.g., so that the sensor ID, time stamp and each axis of the measured data is stored in its own word. Additionally, the bit unpacker may decompress the bit packed sensor data by reinserting the sensor ID and/or time stamp in the sensor data.

公开(公告)号：US10148270B2

公开(公告)日：2018-12-04

申请号：US15658206

申请日：2017-07-24

Applicant: QuickLogic Corporation

Inventor： Pinaki Chakrabarti ,  Wilma W. Shiao ,  Ket-Chong Yap ,  Vishnu A. Patil ,  Lalit Narain Sharma

IPC: H03K19/177 ,  G06F17/50

Abstract: A programmable logic device uses power island based design partitioning. Each power islands includes a plurality of programmable logic cells and a programmable routing network configurable to interconnect the plurality of programmable logic cells and configurable to interconnect with at least one other power island. When a power island is in an OFF state, the programmable logic cells within the power island are powered OFF. Feed-through routing connectors in the power island, however, may be statically or dynamically powered ON independently of the powered OFF state of the power island.

公开(公告)号：US09287868B1

公开(公告)日：2016-03-15

申请号：US14476515

申请日：2014-09-03

Applicant: QuickLogic Corporation

Inventor： Vishnu A. Patil ,  Wilma W. Shiao ,  Tarachand Pagarani ,  Pinaki Chakrabarti

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/0008 ,  H03K19/017581 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774

Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.

Abstract translation: 可编程逻辑器件中的逻辑单元从路由网络接收外部信号，该路由网络充当通过第一多路复用器选择组合逻辑信号的选择信号以及输入到第二多路复用器的数据。 第二复用器在组合逻辑信号和外部信号之间进行选择，并向寄存器提供输出信号。 因此，逻辑单元具有使用最小路由资源来支持组合和/或顺序功能的灵活性。 第三多路复用器可以选择来自寄存器或另一信号的输出作为来自逻辑单元的输出信号。 当寄存器输出未被选择作为输出信号时，到寄存器的时钟信号可能被关闭，从而降低动态功耗。 可编程逻辑器件可以包括多个超级逻辑单元，每个超级逻辑单元包括多个逻辑单元。

公开(公告)号：US09118325B1

公开(公告)日：2015-08-25

申请号：US14476518

申请日：2014-09-03

Applicant: QuickLogic Corporation

Inventor： Vishnu A. Patil ,  Karyampoodi Bhanu Prasanth ,  Wilma W. Shiao ,  Tarachand Pagarani ,  Pinaki Chakrabarti

IPC: H03K19/177 ,  H03K19/0175

CPC classification number: H03K19/0008 ,  H03K19/017581 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774

Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway and clock networks. Some of the switches include multiple stages. The feedback network switch receives signals from the logic island as well as from neighboring logic blocks and provides an output to one or more stages of the street network switch. The street network switch receives the signals from the feedback network switch and signals from neighboring highway network switches and provides an output to the logic island. A clock network switch may receive dedicated clock signals or high fan out signals as inputs and provides outputs to the street network switch. The highway network switch receives signals from the logic island and from neighboring highway network switches and provides an output to neighboring highway network switches.

Abstract translation: 路由网络与可编程逻辑设备的逻辑块中的逻辑岛相关联，并且包括用于反馈，街道和高速公路和时钟网络中的每一个的交换机。 一些交换机包括多个阶段。 反馈网络交换机从逻辑岛以及相邻逻辑块接收信号，并向街道网络交换机的一个或多个阶段提供输出。 街道网络交换机接收来自反馈网络交换机的信号和来自相邻公路网络交换机的信号，并向逻辑岛提供输出。 时钟网络交换机可以接收专用时钟信号或高扇出输出信号作为输入，并向街道交换机提供输出。 高速公路网络交换机接收来自逻辑岛的信号和相邻的公路网络交换机的信号，并向邻近的公路网络交换机提供输出。

公开(公告)号：US08487652B2

公开(公告)日：2013-07-16

申请号：US13212522

申请日：2011-08-18

Applicant: Ket-Chong Yap ,  Senani Gunaratna ,  Wilma Waiman Shiao

Inventor： Ket-Chong Yap ,  Senani Gunaratna ,  Wilma Waiman Shiao

IPC: H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.

Abstract translation: 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。

公开(公告)号：US20080133988A1

公开(公告)日：2008-06-05

申请号：US11565441

申请日：2006-11-30

Applicant: Stephen U. Yao ,  Darwin D.Q. Samson ,  Ket-Chong Yap

Inventor： Stephen U. Yao ,  Darwin D.Q. Samson ,  Ket-Chong Yap

IPC: G01R31/28

CPC classification number: G01R31/318516

Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic.

Abstract translation: 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑，从而提供组合逻辑的测试。

公开(公告)号：US20050127885A1

公开(公告)日：2005-06-16

申请号：US10738382

申请日：2003-12-16

Applicant: Soon-Gil Jung

Inventor： Soon-Gil Jung

IPC: G05F1/40 ,  G05F1/565 ,  H03F1/38

CPC classification number: H03F1/38 ,  G05F1/565

Abstract: A voltage regulator with a variable compensation capacitor is capable of driving a large variable dynamic current load. The regulator includes an error amplifier and an output stage amplifier. The variable compensation capacitor is disposed between the output terminal of the error amplifier and the output terminal of the output stage amplifier. In one embodiment, a NMOS transistor is disposed between the output terminal of the output stage amplifier and the variable compensation capacitor. The variable compensation capacitor may be, e.g., a PMOS transistor with the source and drain tied together. In one embodiment, a plurality of regulators is included on chip, e.g., such as a programmable device, where the output terminals of each regulator is tied together and used to drive the same load.

Abstract translation: 具有可变补偿电容器的电压调节器能够驱动大的可变动态电流负载。 调节器包括误差放大器和输出级放大器。 可变补偿电容器设置在误差放大器的输出端和输出级放大器的输出端之间。 在一个实施例中，NMOS晶体管设置在输出级放大器的输出端和可变补偿电容之间。 可变补偿电容器可以是例如将源极和漏极连接在一起的PMOS晶体管。 在一个实施例中，多个调节器包括在芯片上，例如可编程器件，其中每个调节器的输出端子被连接在一起并用于驱动相同的负载。

公开(公告)号：US6150199A

公开(公告)日：2000-11-21

申请号：US405979

申请日：1999-09-27

Applicant: Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

Inventor： Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。