公开(公告)号：US09118325B1

公开(公告)日：2015-08-25

申请号：US14476518

申请日：2014-09-03

Applicant: QuickLogic Corporation

Inventor： Vishnu A. Patil ,  Karyampoodi Bhanu Prasanth ,  Wilma W. Shiao ,  Tarachand Pagarani ,  Pinaki Chakrabarti

IPC: H03K19/177 ,  H03K19/0175

CPC classification number: H03K19/0008 ,  H03K19/017581 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774

Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway and clock networks. Some of the switches include multiple stages. The feedback network switch receives signals from the logic island as well as from neighboring logic blocks and provides an output to one or more stages of the street network switch. The street network switch receives the signals from the feedback network switch and signals from neighboring highway network switches and provides an output to the logic island. A clock network switch may receive dedicated clock signals or high fan out signals as inputs and provides outputs to the street network switch. The highway network switch receives signals from the logic island and from neighboring highway network switches and provides an output to neighboring highway network switches.

Abstract translation: 路由网络与可编程逻辑设备的逻辑块中的逻辑岛相关联，并且包括用于反馈，街道和高速公路和时钟网络中的每一个的交换机。 一些交换机包括多个阶段。 反馈网络交换机从逻辑岛以及相邻逻辑块接收信号，并向街道网络交换机的一个或多个阶段提供输出。 街道网络交换机接收来自反馈网络交换机的信号和来自相邻公路网络交换机的信号，并向逻辑岛提供输出。 时钟网络交换机可以接收专用时钟信号或高扇出输出信号作为输入，并向街道交换机提供输出。 高速公路网络交换机接收来自逻辑岛的信号和相邻的公路网络交换机的信号，并向邻近的公路网络交换机提供输出。