Invention Grant
- Patent Title: Method for fabrication of programmable interconnect structure
- Patent Title (中): 可编程互连结构的制造方法
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Application No.: US405979Application Date: 1999-09-27
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Publication No.: US6150199APublication Date: 2000-11-21
- Inventor: Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
- Applicant: Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
- Applicant Address: CA Sunnyvale
- Assignee: QuickLogic Corporation
- Current Assignee: QuickLogic Corporation
- Current Assignee Address: CA Sunnyvale
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L23/525 ; H01L27/10
Abstract:
In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
Public/Granted literature
- US5714582A Invertebrate type V telopeptide collagen, methods of making, and use thereof Public/Granted day:1998-02-03
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