公开(公告)号：US11714752B2

公开(公告)日：2023-08-01

申请号：US17702505

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/205 ,  G11C14/0018

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US11704192B2

公开(公告)日：2023-07-18

申请号：US17236444

申请日：2021-04-21

Applicant: Pure Storage, Inc.

Inventor： Andrew R. Bernat ,  Matthew Paul Fay ,  Ronald Karr

IPC: G06F11/10 ,  G06F12/0804

CPC classification number: G06F11/1048 ,  G06F12/0804 ,  G06F2212/1032

Abstract: A storage system has zones in solid-state storage memory, with power loss protection. The system identifies portions of data for processes that utilize power loss protection. The system determines to activate or deactivate power loss protection for the portions of data for the processes. The system tracks activation and deactivation of power loss protection in zones in the solid-state storage memory, in accordance with the portions of data having power loss protection activated or deactivated.

公开(公告)号：US20230222066A1

公开(公告)日：2023-07-13

申请号：US17572245

申请日：2022-01-10

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Naga P. Gorti ,  Guy L. Guthrie ,  Sanjeev Ghai

IPC: G06F12/0862 ,  G06F12/0871 ,  G06F12/0817 ,  G06F12/0804

CPC classification number: G06F12/0862 ,  G06F12/0871 ,  G06F12/0817 ,  G06F12/0804 ,  G06F2212/1021

Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.

公开(公告)号：US11681624B2

公开(公告)日：2023-06-20

申请号：US16931490

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik ,  George Patsilaras

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/10

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/657

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

公开(公告)号：US11681619B2

公开(公告)日：2023-06-20

申请号：US17464088

申请日：2021-09-01

Applicant: SK hynix Inc.

Inventor： Jong-Min Lee

IPC: G06F12/0804 ,  G06F12/06

CPC classification number: G06F12/0804 ,  G06F12/0646 ,  G06F2212/1032

Abstract: A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

公开(公告)号：US11675517B2

公开(公告)日：2023-06-13

申请号：US17969296

申请日：2022-10-19

Applicant: Google LLC

Inventor： Mohsen Vakilian ,  Hossein Ahmadi

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0804

CPC classification number: G06F3/0644 ,  G06F3/067 ,  G06F3/0611 ,  G06F12/0223 ,  G06F12/0804

Abstract: A system and method for repartitioning data in a distributed network. The method may include executing, by one or more processors, a first pass of a data set from a plurality of first sources to a plurality of first sinks, each first sink collecting data from one or more of the first sources, and executing, by the one or more processors, a second pass of the data set from a plurality of second sources to a plurality of second sinks, each one of the plurality of first sinks corresponding to one of the plurality of second sources, and each second sink collecting data from one or more of the second sources. Executing the first and second passes causes the data set to be repartitioned such that one or more second sinks collect data that originated from two or more of the first sources.

公开(公告)号：US11663127B2

公开(公告)日：2023-05-30

申请号：US17469321

申请日：2021-09-08

Applicant: EMC IP Holding Company LLC

Inventor： Geng Han ,  Jian Gao ,  Xinlei Xu ,  Yousheng Liu ,  Jianbin Kang

IPC: G06F12/00 ,  G06F12/0804

CPC classification number: G06F12/0804 ,  G06F2212/1032

Abstract: Techniques for managing a storage system involve flushing a target page in a cache device to a persistent storage device of the storage system. The techniques further involve releasing a resource storing a page descriptor of the target page to a resource pool. The resource pool is configured to provide resources to store page descriptors of pages to be flushed in the cache device. The techniques further involve: if it is determined that an auxiliary descriptor of the target page is located at a tail of a queue of auxiliary descriptors of the pages to be flushed, removing the auxiliary descriptor of the target page from the queue. The auxiliary descriptors of the pages to be flushed are configured to describe the page descriptors of the pages to be flushed. Accordingly, the page flushing performance of the storage system can be improved, thereby improving the input/output performance.

公开(公告)号：US20230117637A1

公开(公告)日：2023-04-20

申请号：US17504863

申请日：2021-10-19

Applicant: Arista Networks, Inc.

Inventor： Fai LI ,  Elliott Benard VAN HARTINGSVELDT

IPC: G06F12/0804 ,  G06F1/30

Abstract: Signals (e.g., power, clock, etc.) that support operation of a processor subsystem in a computer system are supplied by support subsystems in the computer system. Fault logic in the computer system automatically reads out state information from a support subsystem in response to detection of a fault in the support system. The fault logic is separate from the processor subsystem and so can continue to function when a support subsystem fails. The state information contains fault information indicative of the state of the support subsystem at the time of failure. The fault logic stores the state information in non-volatile memory for subsequent analysis.

公开(公告)号：US20230113508A1

公开(公告)日：2023-04-13

申请号：US18080706

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Lien Linus Lu

IPC: G06F12/0804 ,  G06F12/06 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.

公开(公告)号：US11620219B2

公开(公告)日：2023-04-04

申请号：US16953046

申请日：2020-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin J. Ash ,  Matthew G. Borlick ,  Lokesh M. Gupta ,  Trung N. Nguyen

IPC: G06F12/0804 ,  G06F12/121 ,  G06F12/0868

Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.