公开(公告)号：US5940449A

公开(公告)日：1999-08-17

申请号：US642663

申请日：1996-05-03

申请人： Jurgen Kaaden ,  Dietmar Brauer ,  Gerhard Reiner

发明人： Jurgen Kaaden ,  Dietmar Brauer ,  Gerhard Reiner

IPC分类号： G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H03M13/33 ,  H04L7/02 ,  H04L7/033 ,  H03M13/12 ,  H04L7/00

CPC分类号： H04L7/0062 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/18 ,  H03M13/33 ,  H04L7/0334 ,  G11B2220/2516 ,  G11B2220/2562 ,  G11B2220/90

摘要： In digital, magnetic and optical storage systems for audio/video/data, a Viterbi detector is extended by a control output, and a PLL is controlled by a variable delay line at the output or inside of the PLL.

摘要翻译： 在用于音频/视频/数据的数字，磁和光存储系统中，维特比检测器由控制输出扩展，PLL由PLL的输出端或内部的可变延迟线控制。

公开(公告)号：US5930448A

公开(公告)日：1999-07-27

申请号：US841599

申请日：1997-04-30

申请人： Woo-Nyun Lee ,  Hyung-Joo Lee

发明人： Woo-Nyun Lee ,  Hyung-Joo Lee

IPC分类号： H04N5/7826 ,  G11B15/467 ,  G11B20/18 ,  G11B21/10 ,  H03M13/33 ,  H04N5/91

CPC分类号： H03M13/33 ,  G11B15/4676 ,  G11B20/18

摘要： A tracking control circuit is disclosed for use in a digital image recording and reproducing device which has a mechanism (22) for controlling the movement of a magnetic medium according to a servo control signal, which has an error correction code decoder (12), and which reproduces data recorded on the recording medium in sync blocks. The tracking control circuit includes a bit error rate detector (14), a control unit (16, 18) and a servo circuit (20). The bit error rate detector (14) calculates the frequency of bit errors in the reproduced data by counting the number of error flags from the error correction code decoder in each sync block to thereby producing bit error rate data. The control unit (16, 18) generates tracking control data corresponding to bit error rate data generated by the bit error rate detector (14) when the bit error rate data from the bit error rate detector exceeds a predetermined limit. The servo circuit (20) provides a servo control signal corresponding to the tracking control data which is supplied from the control unit (16, 18).

摘要翻译： 公开了一种用于数字图像记录和再现装置的跟踪控制电路，其具有用于根据具有纠错码解码器（12）的伺服控制信号控制磁性介质的移动的机构（22），以及 其再现记录在记录介质上的同步块中的数据。 跟踪控制电路包括误码率检测器（14），控制单元（16,18）和伺服电路（20）。 误码率检测器（14）通过对来自每个同步块中的纠错码解码器的错误标志数进行计数来计算再现数据中的位错误的频率，从而产生误码率数据。 当来自误码率检测器的误码率数据超过预定极限时，控制单元（16,18）产生对应于由位错误率检测器（14）产生的误码率数据的跟踪控制数据。 伺服电路（20）提供与从控制单元（16,18）提供的跟踪控制数据对应的伺服控制信号。

公开(公告)号：US5809044A

公开(公告)日：1998-09-15

申请号：US675517

申请日：1996-06-27

申请人： Toshiya Todoroki

发明人： Toshiya Todoroki

IPC分类号： H03M13/33 ,  H03M13/41 ,  H04L7/00 ,  H04L7/04 ,  H04L7/08 ,  H04L25/08 ,  G06F11/10

CPC分类号： H04L7/048 ,  H03M13/33

摘要： A branch value output circuit checks a preceding state to which a maximum path metric state determined in a Viterbi decoding process by a Viterbi decoder has transited, uses the maximum path metric state, and determines a branch value between transitions. A correlator determines a correlation in each interval between the branch value and soft-decided received data and outputs a correlative value representing the correlation in each interval. A synchronism/asynchronism determining circuit determines whether the received data are in a synchronous or asynchronous condition based on the correlative value in each interval. If the received data are determined to be in an asynchronous condition by the synchronism/asynchronism determining circuit, the synchronism/asynchronism determining circuit supplies a phase control signal to a phase converter. The phase converter changes the phase of the received data in response to the phase control signal. Therefore, it can be detected whether the soft-decided received data are in the synchronous or asynchronous condition, and if the received data are in the asynchronous condition, the received data are controlled into the synchronous condition.

摘要翻译： 分支值输出电路检查由维特比解码器在维特比解码处理中确定的最大路径度量状态已经过渡的先前状态，使用最大路径度量状态，并确定转换之间的分支值。 相关器确定分支值和软判决接收数据之间的每个间隔中的相关性，并输出表示每个间隔中的相关性的相关值。 同步/异步确定电路基于每个间隔中的相关值来确定接收的数据是处于同步还是异步状态。 如果通过同步/异步确定电路将接收到的数据确定为异步状态，则同步/异步确定电路将相位控制信号提供给相位转换器。 相位转换器响应于相位控制信号改变接收数据的相位。 因此，可以检测软判决接收数据是处于同步还是异步状态，如果接收到的数据处于异步状态，则将接收的数据控制为同步状态。

公开(公告)号：US5761249A

公开(公告)日：1998-06-02

申请号：US619300

申请日：1996-03-21

申请人： Nadav Ben-Efraim

发明人： Nadav Ben-Efraim

IPC分类号： H03M13/00 ,  H03M13/27 ,  H03M13/33 ,  H04L7/04 ,  H04L27/06 ,  H04L7/00

CPC分类号： H03M13/2732 ,  H03M13/00 ,  H03M13/33 ,  H04L7/048

摘要： A decoder de-interleaver comprises a de-interleaver for de-interleaving received interleaved encoded data that includes periodic decoder synchronization signals to produce de-interleaved encoded data. A decoder decodes the de-interleaved encoded data to produce output data. The de-interleaver has a latency such that the de-interleaved encoded data is delayed by (B-1) times a period of the decoder synchronization signals plus a constant interval, where B is the interleave depth. A synchronization pulse generator receives the interleaved and encoded data and generates decoder synchronization pulses that are substantially coincident with the decoder synchronization signals. A delay unit is connected between the synchronization pulse generator and the decoder for delaying the decoder synchronization pulses by the constant interval. The decoder thereby receives decoder synchronization pulses that correspond to previous decoder synchronization signals, but functions properly because the relative timing is correct. The decoder has an error detecting function by which the first B-1 decoder synchronization pulses that are generated before the de-interleaver produces valid de-interleaved encoded data are ignored.

摘要翻译： 解码器解交织器包括解交织器，用于对包含周期性解码器同步信号的接收交织编码数据进行解交织以产生解交织编码数据。 解码器对解交织的编码数据进行解码以产生输出数据。 解交织器具有延迟，使得解交织编码数据在解码器同步信号的周期加上恒定间隔延迟（B-1）倍，其中B是交织深度。 同步脉冲发生器接收交织和编码数据并产生与解码器同步信号基本一致的解码器同步脉冲。 延迟单元连接在同步脉冲发生器和解码器之间，用于将解码器同步脉冲延迟恒定间隔。 因此，解码器接收对应于先前的解码器同步信号的解码器同步脉冲，但由于相对定时正确，因此正常工作。 解码器具有错误检测功能，通过该功能，在解交织器产生有效的解交织编码数据之前产生的第一B-1解码器同步脉冲被忽略。

公开(公告)号：US5715259A

公开(公告)日：1998-02-03

申请号：US305789

申请日：1994-09-14

申请人： Bhum Cheol Lee ,  Sung Yeal Im ,  Jung Sik Kim

发明人： Bhum Cheol Lee ,  Sung Yeal Im ,  Jung Sik Kim

IPC分类号： H03M13/00 ,  H03M13/09 ,  H03M13/33 ,  H04L1/00 ,  H04L7/00 ,  G06F11/10

CPC分类号： H03M13/091 ,  H03M13/33

摘要： A cyclic redundancy check synchronizer includes an N-byte shift register for shifting an input byte string by N bytes and N-1 bytes, a compensation polynomial driver for driving a compensation polynomial by modulo-2-dividing bits of a byte output from the Nth stage of the N-byte shift register by a generator polynomial and shifting the resultant remainder by one bit in a direction toward higher-order bits, and a calculator for inputting bits of an output byte from a remainder register as high-order bits and bits of an input data byte as low-order bits and for performing compensation polynomial modulo-2 subtraction and generator polynomial modulo-2 division for the inputted bits. The cyclic redundancy check synchronizer also includes a block synchronization identifier for searching for syndrome output signals from the calculator at an interval of a byte time to check whether the same syndrome signal is outputted from the calculator successively a predetermined number of times or more at an interval of a block period, and a data selector for selecting bits constituting a byte from among output bits from the N-byte shift register according to a certain one of the syndrome output signals from the calculator resulting in a block synchronous state in response to a data selection signal from the block synchronization identifier to output byte-synchronized data.

摘要翻译： 循环冗余校验同步器包括用于将输入字节串移位N字节和N-1字节的N字节移位寄存器，用于通过对从第N个字节输出的字节的模数进行模2分频来驱动补偿多项式的补偿多项式驱动器 通过生成多项式将N字节移位寄存器的阶段移位，并将结果余数沿朝向高阶位的方向移位一位，以及用于将来自余数寄存器的输出字节的位输入为高位位和位的计算器 输入数据字节作为低位比特，并用于对输入的比特执行补偿多项式模2减法和生成多项式模2除法。 循环冗余校验同步器还包括块同步标识符，用于以一个字节时间的间隔搜索来自计算器的校正子输出信号，以检查是否从计算器以一定间隔连续输出预定次数或更多次的校正子信号 以及数据选择器，用于根据来自所述计算器的所述校正子输出信号中的某一个从所述N字节移位寄存器的输出位中选择构成字节的位，以响应于数据产生块同步状态 来自块同步标识符的选择信号输出字节同步数据。

公开(公告)号：US5481568A

公开(公告)日：1996-01-02

申请号：US361451

申请日：1994-12-21

申请人： Hiroaki Yada

发明人： Hiroaki Yada

IPC分类号： G11B20/10 ,  G11B20/14 ,  H03K5/08 ,  H03L7/091 ,  H03M13/00 ,  H03M13/33 ,  H04L7/02 ,  H04L25/06 ,  H04L27/00 ,  H03D1/00

CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  H04L25/068 ,  H04L7/0029 ,  H04L7/0334

摘要： A data detecting apparatus for detecting desired data from a digital signal comprising a first sampling circuit for sampling the digital signal to output samples, an interpolating circuit for interpolating signal values between the samples outputted from the first sampling circuit, and a second sampling circuit for extracting those signal values interpolated by the interpolating circuit which match a phase of a point at which the desired data exists. This constitution allows to implement all blocks making up the data detecting apparatus with digital signal processing circuits synchronously operating on the a clock, detecting the reproduced signal data without being affected by jitters contained in reproduced signals coming from a channel. The constitution also makes it possible to form on a single LSI chip such circuits including the data detecting apparatus, an ECC decoder, a controller, and an interface circuit as conventionally formed on discrete chips. This permits a compact implementation of an entire apparatus and reduces its production cost. Further, this constitution facilitates the design and test for implementing the embodiment on large scale integrations and eliminates the necessity for externally attached analog parts, making the implementation free of adjustment and less susceptible to aging.

摘要翻译： 一种用于从数字信号中检测所需数据的数据检测装置，包括用于对数字信号进行采样以输出样本的第一采样电路，用于内插从第一采样电路输出的采样之间的信号值的内插电路和用于提取的第二采样电路 通过内插电路内插的与所需数据存在的点的相位匹配的那些信号值。 这种结构允许利用在时钟上同步工作的数字信号处理电路来实现构成数据检测装置的所有块，检测再现的信号数据而不受来自信道的再现信号中包含的抖动的影响。 该结构还使得可以在单个LSI芯片上形成包括数据检测装置，ECC解码器，控制器和如在离散芯片上传统地形成的接口电路的电路。 这允许整个设备的紧凑实现并且降低其生产成本。 此外，该结构有助于实现大规模集成的实施例的设计和测试，并且消除了对外部连接的模拟部件的需要，使得实现不受调节并且不易老化。

公开(公告)号：US5220568A

公开(公告)日：1993-06-15

申请号：US433877

申请日：1989-11-09

申请人： Dennis G. Howe ,  Edward J. Weldon, Jr. ,  Hugh M. Hilden

发明人： Dennis G. Howe ,  Edward J. Weldon, Jr. ,  Hugh M. Hilden

IPC分类号： G11B20/10 ,  H03M5/14 ,  H03M13/27 ,  H03M13/29 ,  H03M13/31 ,  H03M13/33 ,  H04L7/04

CPC分类号： H03M13/2703 ,  H03M13/152 ,  H03M13/29 ,  H03M13/31 ,  H03M13/33 ,  H03M5/145 ,  H04L7/048 ,  G11B20/10212 ,  H04L7/041

摘要： Channel encoded data (for example run length limited encoded data) is further encoded in accordance with a shift correction code prior to transmission. Upon reception, forward and backward shift errors present in the received channel encoded data are corrected by a shift correction decoder. The shift error correction is accomplished using a code, such as (for example) a BCH code over GF(p) or a negacyclic code, which treats each received symbol as a vector having p states. For a single shift error correction, p=3 and there are three states (forward shift, backward shift, no shift). In one embodiment, conventional error correction codewords which encode the user data may be interleaved within successive shift correction codewords prior to channel encoding, thereby enabling the error correction system to easily handle a high rate of randomly distributed shift errors (which otherwise would result in a high rate of short error bursts that exceed the capacity of the block error correction code).

摘要翻译： 通道编码数据（例如游程长度限制编码数据）在传输之前根据移位校正码被进一步编码。 在接收时，通过移位校正解码器校正存在于接收信道编码数据中的前向和后向移位误差。 使用诸如（例如）GF（p）上的BCH码或者负循环码的代码来实现移位误差校正，其将每个接收到的符号视为具有p个状态的向量。 对于单次移位误差校正，p = 3，并且有三种状态（前向移位，后向移位，无移位）。 在一个实施例中，编码用户数据的常规纠错码字可以在信道编码之前的连续移位校正码字中进行交织，从而使得纠错系统能够容易地处理高速随机分布的移位误差（否则将导致 高错误突发速率超过块错误校正码的容量）。

公开(公告)号：US4853930A

公开(公告)日：1989-08-01

申请号：US099801

申请日：1987-09-22

申请人： Michio Shimada

发明人： Michio Shimada

IPC分类号： H03M13/33 ,  H03M13/39

CPC分类号： H03M13/39 ,  H03M13/33

摘要： In an encoder replica of a decoder for an input code sequence which corresponds to a code symbol sequence comprising an information symbol sequence and a redundancy bit sequence, a one-bit memory (46) successively memorizes consecutive bits of the input code sequence as memorized bits. An output circuit (62) delivers replica output bits in bit series to a sequential decode controller (43) in response to the memorized bits. In response to the memorized bits and a control signal produced by the controller in response to the input code sequence and the replica output bits, the encoder replica decodes the input code sequence into a reproduction of the information symbol sequence. Preferably, the output circuit is controlled by a position counter (64) giving separate indication of bits corresponding in the input code sequence to the information symbol sequence and of bits corresponding in the input code sequence to the redundancy bit sequence. More preferably, a synchronism shift counter corrects the separate indication in consideration of a shift in synchronism of the separate indication relative to the input code sequence.

摘要翻译： 在对应于包括信息符号序列和冗余位序列的码符号序列的用于输入码序列的解码器的编码器副本中，一位存储器（46）将输入码序列的连续比特顺序存储为存储位 。 响应于存储的位，输出电路（62）以位串的形式将副本输出位传送到顺序解码控制器（43）。 响应于存储的位和由控制器响应于输入代码序列和副本输出位而产生的控制信号，编码器副本将输入代码序列解码为信息符号序列的再现。 优选地，输出电路由位置计数器（64）控制，该位置计数器（64）给输入代码序列中对应的比特的单独指示信息符号序列以及与输入代码序列相对应的位相对于冗余比特序列。 更优选地，同步移位计数器考虑到单独指示相对于输入代码序列的同步偏移来校正单独的指示。

公开(公告)号：US4821270A

公开(公告)日：1989-04-11

申请号：US937596

申请日：1986-12-03

申请人： Jacques Mauge

发明人： Jacques Mauge

IPC分类号： H04B7/26 ,  G08G1/09 ,  H03M13/00 ,  H03M13/33 ,  H04H60/11 ,  H04L1/00 ,  H04L7/04 ,  G06F11/00

CPC分类号： H04H60/11 ,  G08G1/092 ,  H03M13/33 ,  H04L1/0045 ,  H04L1/0057 ,  H04L7/048 ,  H04H2201/13

摘要： Method of decoding data making it possible to correct certain errors, e.g. in synchronization and transmission. The method relates to decoding data transmitted in groups of blocks. Each block has n1+n2 bits, where n1 is the length of a corresponding information word. The information word is extended to an error protection block of n1+n2 bits by application of a linear error protection code and an off-set which indicates the position of the block within a group. Synchronization is established by incremental generation of a position-indicating syndrome from the block. If error correction is found to be necessary, it begins after synchronization. Synchronization is restarted if too many errors occur. A device for implementing the method includes a radio receiver (21), a microprocessor (22) for its control and a universal decoder (11) consisting on the one hand of a demodulation (13) and clock regeneration (12) component, the input of which is connected to the multiplex output of the radio receiver (21) and, on the other, of a broadcast data processing microprocessor (14), the output of which is connected to said microprocessor (22) for controlling the radio receiver.

摘要翻译： 解码数据的方法可以纠正某些错误，例如 同步和传输。 该方法涉及对以块为单位发送的数据进行解码。 每个块具有n1 + n2位，其中n1是相应信息字的长度。 信息字通过应用线性错误保护代码和表示块在组内的位置的偏移来扩展到n1 + n2位的错误保护块。 通过从块增加生成位置指示综合征来建立同步。 如果发现纠错是必要的，则在同步后开始。 如果发生太多错误，则重新启动同步。 用于实现该方法的装置包括无线电接收器（21），用于其控制的微处理器（22）和一方面由解调（13）和时钟再生（12）组件构成的通用解码器（11） 其连接到无线电接收器（21）的多路复用输出，另一方面连接到广播数据处理微处理器（14），该广播数据处理微处理器的输出端连接到用于控制无线电接收机的所述微处理器（22）。

公开(公告)号：US4747105A

公开(公告)日：1988-05-24

申请号：US903335

申请日：1986-09-03

申请人： Alan L. Wilson ,  Michael W. Bright ,  Eric F. Ziolko

发明人： Alan L. Wilson ,  Michael W. Bright ,  Eric F. Ziolko

IPC分类号： H03M13/33 ,  H04L7/04 ,  G06F11/10

CPC分类号： H03M13/33 ,  H04L7/043 ,  H04L7/048

摘要： A detector locates a shift register sequence within a digital data stream by correlating the data stream with a sequence generated locally from a portion of the data stream. Error correction circuitry estimates errors that may have corrupted the sequence during transmission across a noisy channel and corrects them to the extent possible. The data stream and local sequence are correlated during an interval that is shifted either ahead or behind the portion of the error-corrected data stream used to initialize the local sequence generator, thereby avoiding the region during which short-term correlation between the data stream and local sequence would otherwise cause false indications of detection when only noise or random data is being received.

摘要翻译： 检测器通过将数据流与从数据流的一部分本地生成的序列相关联来定位数字数据流内的移位寄存器序列。 误差校正电路估计可能在穿过嘈杂信道的传输期间损坏序列的错误，并尽可能地校正它们。 数据流和本地序列在被用于初始化本地序列发生器的纠错数据流的部分之前或之后移动的间隔期间相关，从而避免数据流和数据流之间的短期相关性 否则当仅接收到噪声或随机数据时，本地序列将导致错误的检测指示。