公开(公告)号：US09419221B2

公开(公告)日：2016-08-16

申请号：US14303333

申请日：2014-06-12

Applicant: SK hynix Inc.

Inventor： Se Hun Kang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/124 ,  H01L45/1683

Abstract: A method of fabricating a semiconductor integrated circuit that includes forming a lower electrode in a semiconductor substrate, forming an interlayer insulating layer including a phase-change region exposing the lower electrode on the semiconductor substrate, forming a first phase-change layer having a crystalline state along surfaces of the interlayer insulating layer and an exposed lower electrode, and growing a second phase-change layer on the first phase-change layer based on the crystallinity of the first phase-change layer to be filled in the phase-change region.

Abstract translation: 一种制造半导体集成电路的方法，包括在半导体衬底中形成下电极，形成包括在半导体衬底上暴露下电极的相变区的层间绝缘层，形成具有结晶态的第一相变层 沿着层间绝缘层的表面和暴露的下电极，并且基于要填充在相变区域中的第一相变层的结晶度，在第一相变层上生长第二相变层。

公开(公告)号：US20160218284A1

公开(公告)日：2016-07-28

申请号：US14729181

申请日：2015-06-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Chien-Hung Lu ,  Chin-Yi Tseng

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633 ,  H01L45/1683

Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.

Abstract translation: 提供了包括绝缘层，第一电极层和第一屏障的存储结构。 绝缘层具有凹部。 第一电极层形成在凹部中并且具有第一顶表面。 第一阻挡层形成在绝缘层和第一电极层之间，并且具有比第一顶表面低的第二顶表面。 第一顶表面和第二顶表面比凹口的开口低。

公开(公告)号：US20160218147A1

公开(公告)日：2016-07-28

申请号：US14967025

申请日：2015-12-11

Applicant: HGST, Inc.

Inventor： Daniel Robert SHEPARD

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1683

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract translation: 一种用于制造3-D交叉点存储器阵列的方法，更具体地说涉及制造具有4F2单元尺寸占空比的相变存储器（PCM）和电阻RAM（ReRAM或RRAM）3-D存储器阵列。 使用有限数量的光刻图案化步骤形成多层存储单元的方法适用于每个单元具有单个或多个存储位的存储器件，例如每个单元或更多个单元具有1至8位的单元。 这些位三维堆叠，并且包括基于相变材料的存储器单元，电阻变化材料，磁场对准，机械开关以及基于其他信息存储技术的其它存储器单元。

公开(公告)号：US20160190444A1

公开(公告)日：2016-06-30

申请号：US15064610

申请日：2016-03-09

Applicant: Powerchip Technology Corporation

Inventor： Mao-Teng Hsu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1616 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

Abstract: A resistive random access memory (RRAM) including a substrate, a dielectric layer, memory cells and an interconnect structure is provided. The dielectric layer is disposed on the substrate. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first electrode, a second electrode and a variable resistance structure. The second electrode is disposed on the first electrode. The variable resistance structure is disposed between the first electrode and the second electrode. In two vertically adjacent memory cells, the first electrode of the upper memory cell and the second electrode of the lower memory cell are disposed between the adjacent variable resistance structures and isolated from each other. The interconnect structure is disposed in the dielectric layer and connects the first electrodes of the memory cells.

Abstract translation: 提供了包括基板，电介质层，存储单元和互连结构的电阻随机存取存储器（RRAM）。 电介质层设置在基板上。 存储单元垂直并相邻地布置在电介质层中，并且每个存储单元包括第一电极，第二电极和可变电阻结构。 第二电极设置在第一电极上。 可变电阻结构设置在第一电极和第二电极之间。 在两个垂直相邻的存储单元中，上存储单元的第一电极和下存储单元的第二电极设置在相邻的可变电阻结构之间并彼此隔离。 互连结构设置在电介质层中并连接存储单元的第一电极。

公开(公告)号：US20160181519A1

公开(公告)日：2016-06-23

申请号：US15059489

申请日：2016-03-03

Applicant: Sony Corporation

Inventor： Scott Sills ,  Beth Cook ,  Nirmal Ramaswamy

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1683

Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.

公开(公告)号：US09373788B2

公开(公告)日：2016-06-21

申请号：US14185427

申请日：2014-02-20

Applicant: SK hynix Inc.

Inventor： Young Seok Kwon ,  Kwon Hong

IPC: H01L21/06 ,  H01L45/00 ,  C23C16/30 ,  C23C16/455

CPC classification number: H01L45/1616 ,  C23C16/305 ,  C23C16/45523 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

Abstract: A method for fabricating a semiconductor device includes supplying a first source gas including a germanium (Ge) precursor onto a semiconductor substrate for a first time period, and periodically interrupting the supplying of the first source gas for the first time period to form Ge elements on the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括：将包含锗（Ge）前体的第一源气体在第一时间段内提供到半导体衬底上，并且周期性地中断第一时间段内的第一源气体的供应以形成Ge元素 半导体衬底。

公开(公告)号：US09373784B2

公开(公告)日：2016-06-21

申请号：US14669776

申请日：2015-03-26

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Jia Xu ,  GuanPing Wu ,  Chao Zhang ,  Daisy Liu

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

Abstract: A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element.

公开(公告)号：US09343677B2

公开(公告)日：2016-05-17

申请号：US14596666

申请日：2015-01-14

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe, III ,  Gurtej S. Sandhu

IPC: G11C11/34 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/165 ,  G11C13/0007 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1683

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

公开(公告)号：US09331279B2

公开(公告)日：2016-05-03

申请号：US14702374

申请日：2015-05-01

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

公开(公告)号：US09306166B1

公开(公告)日：2016-04-05

申请号：US14683945

申请日：2015-04-10

Applicant: SK hynix Inc.

Inventor： Jun Kwan Kim ,  Young Ho Lee ,  Su Jin Chae

IPC: H01L45/00

CPC classification number: H01L45/1641 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A fabrication method of a resistance variable memory apparatus includes forming an amorphous phase-change material layer on a semiconductor substrate in which a bottom structure is formed, and performing crystallization on the amorphous phase-change material layer through a low-temperature plasma treatment process.

Abstract translation: 电阻可变存储装置的制造方法包括：在形成有底部结构的半导体衬底上形成非晶相变材料层，并通过低温等离子体处理工艺在非晶相变材料层上进行结晶化。