公开(公告)号：US11769795B2

公开(公告)日：2023-09-26

申请号：US17499410

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L21/762 ,  H10B12/00

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H10B12/053 ,  H10B12/31 ,  H10B12/34

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US20150357568A1

公开(公告)日：2015-12-10

申请号：US14830077

申请日：2015-08-19

Applicant: Micron Technology, Inc.

Inventor： Joseph N. Greeley ,  John A. Smythe, III

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

Abstract translation: 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。

公开(公告)号：US20150200360A1

公开(公告)日：2015-07-16

申请号：US14596666

申请日：2015-01-14

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe, III ,  Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: H01L45/165 ,  G11C13/0007 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1683

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

Abstract translation: 本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。 形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。 将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。 上电极形成在第一部分上。

公开(公告)号：US20140319446A1

公开(公告)日：2014-10-30

申请号：US14263366

申请日：2014-04-28

Applicant: Micron Technology, Inc.

Inventor： Joseph N. Greeley ,  John A. Smythe, III

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

Abstract translation: 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。

公开(公告)号：US09634250B2

公开(公告)日：2017-04-25

申请号：US15198916

申请日：2016-06-30

Applicant: Micron Technology, Inc.

Inventor： Joseph N. Greeley ,  John A. Smythe, III

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

公开(公告)号：US09514976B2

公开(公告)日：2016-12-06

申请号：US14190801

申请日：2014-02-26

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  John A. Smythe, III

IPC: H01L21/762 ,  H01L27/108 ,  G11C11/401 ,  H01L27/115

CPC classification number: H01L21/76237 ,  G11C11/401 ,  H01L27/10844 ,  H01L27/11517

Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

Abstract translation: 本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。 实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。 在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。 实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

公开(公告)号：US09142770B2

公开(公告)日：2015-09-22

申请号：US14263366

申请日：2014-04-28

Applicant: Micron Technology, Inc.

Inventor： Joseph N. Greeley ,  John A. Smythe, III

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

Abstract translation: 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。

公开(公告)号：US20130099189A1

公开(公告)日：2013-04-25

申请号：US13691352

申请日：2012-11-30

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  John A. Smythe, III

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1658

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.

Abstract translation: 本文描述了电阻存储器和处理电阻性存储器的方法。 处理电阻性存储器的一个或多个方法实施例包括在层间电介质的开口中共形形成电池材料，使得在电池材料中形成接缝，通过改变接缝形成导电通路，并在电池材料上形成电极 和接缝。

公开(公告)号：US20220223602A1

公开(公告)日：2022-07-14

申请号：US17705680

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe, III

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

公开(公告)号：US11239117B1

公开(公告)日：2022-02-01

申请号：US17004084

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Scott E. Sills

IPC: H01L21/8234 ,  H01L21/822 ,  H01L29/66 ,  H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L21/02 ,  H01L27/06

Abstract: Systems, methods, and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material to form a vertical stack. A first vertical opening is formed through the vertical stack to expose a first region of the sacrificial semiconductor material. The first region is selectively removed to form a first horizontal opening in which to replace a sacrificial gate dielectric material, form a source/drain conductive contact material, a channel conductive material, and a digit line conductive contact material of the three-node access device.