公开(公告)号：US20120008411A1

公开(公告)日：2012-01-12

申请号：US13041340

申请日：2011-03-04

Applicant: Gerald J. BANKS

Inventor： Gerald J. BANKS

IPC: G11C16/10

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.

Abstract translation: 通过产生具有构成存储器状态边界的电平的读取参考信号来划分多比特存储器单元的存储器状态。 读取的参考信号可以取决于用于控制存储器单元的编程的编程参考信号的电平。 因此，可以在编程过程期间对存储单元进行编程而不读出其存储状态，通过读取的参考信号对编程参考信号的依赖来确保编程余量。 两组参考信号可以由参考单元产生，该参考单元跟踪诸如温度和系统电压等条件的改变来跟踪存储单元的工作特性的变化，以增强存储器编程和读出的可靠性。

公开(公告)号：US08054692B2

公开(公告)日：2011-11-08

申请号：US12472639

申请日：2009-05-27

Applicant: Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

Inventor： Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C7/02 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.

Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。

公开(公告)号：US20110222342A1

公开(公告)日：2011-09-15

申请号：US13040295

申请日：2011-03-04

Applicant: Sangyong Yoon ,  Kitae Park ,  Jinman Han ,  Wonseok Lee

Inventor： Sangyong Yoon ,  Kitae Park ,  Jinman Han ,  Wonseok Lee

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.

Abstract translation: 数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控​​制器。 数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。 当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列执行主程序操作，并且当需要存储单元阵列的主程序操作时， 存储单元阵列中的主程序操作的程序模式。 该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

公开(公告)号：US07952933B2

公开(公告)日：2011-05-31

申请号：US12632203

申请日：2009-12-07

Applicant: Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

Inventor： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract translation: 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

公开(公告)号：US20110122701A1

公开(公告)日：2011-05-26

申请号：US13019048

申请日：2011-02-01

Applicant: Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

Inventor： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC: G11C16/04

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

公开(公告)号：US07948802B2

公开(公告)日：2011-05-24

申请号：US11999359

申请日：2007-12-04

Applicant: Vishal Sarin ,  Jung Sheng Hoei ,  Frankie F. Roohpavar ,  Giulio-Giuseppe Marotta

Inventor： Vishal Sarin ,  Jung Sheng Hoei ,  Frankie F. Roohpavar ,  Giulio-Giuseppe Marotta

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C7/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.

Abstract translation: 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将斜波电压施加到存储器单元的控制栅极和模数转换器（ADC）。 上述方法的实施例还包括响应于斜坡电压何时使存储器单元跳闸感测电路至少部分地检测ADC的输出。

公开(公告)号：US07929348B2

公开(公告)日：2011-04-19

申请号：US12512829

申请日：2009-07-30

Applicant: Koji Hosono

Inventor： Koji Hosono

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5642

Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.

Abstract translation: 非易失性半导体存储器件包括具有串联连接的多个多电平存储单元的存储单元阵列。 多个多级存储器单元形成多个阈值分布，每个阈值分布对应于较低位的状态和高位的状态，其中低位和高位分别构成下部页面和上部页面 。 较低位的状态将阈值分布分为两组，高位的状态进一步将两组中的每一组进行二分。 当对上部页面的存储单元进行编程时，当对下部页面的存储单元进行编程时，较高电位被施加到与所选字线相邻的未选择字线，而不是应用于未选择的字线。

公开(公告)号：US20110080785A1

公开(公告)日：2011-04-07

申请号：US12968087

申请日：2010-12-14

Applicant: You Sung KIM

Inventor： You Sung KIM

IPC: G11C11/34

CPC classification number: G11C11/5621 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data storing operation for storing an input data to the single level cell section and control a second data storing operation for storing the input data stored in the single level section to the multi level cell section during an idle time.

Abstract translation: 公开了多芯片封装器件和相关数据编程方法。 多芯片封装器件包括一个或多个存储器芯片和控制器。 一个或多个存储器芯片包括单级单元部分和多级单元部分。 控制器被配置为控制用于将输入数据存储到单级单元部分的第一数据存储操作，并且在空闲时间期间控制用于将存储在单级部分中的输入数据存储到多级单元部分的第二数据存储操作 。

公开(公告)号：US07889566B2

公开(公告)日：2011-02-15

申请号：US12466616

申请日：2009-05-15

Applicant: Sang-ku Kang

Inventor： Sang-ku Kang

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: A verify voltage may be changed into a plurality of voltage levels based upon a logic state of each of the memory cells and characteristics or logic states of other memory cells (e.g., adjacent) to each of the memory cells.

Abstract translation: 可以基于每个存储器单元的逻辑状态以及与每个存储器单元的其它存储器单元（例如，相邻）的特性或逻辑状态，将验证电压改变为多个电压电平。

公开(公告)号：US20110026332A1

公开(公告)日：2011-02-03

申请号：US12805089

申请日：2010-07-12

Applicant: Makoto Kitagawa

Inventor： Makoto Kitagawa

IPC: G11C7/10

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5642 ,  G11C2213/79

Abstract: Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a data latch circuit having a second data holding node and a first data holding node connected to the sense line; and a second switch for controlling connection of the second data holding node of the data latch circuit to the bit line.

Abstract translation: 本文公开了一种半导体存储器件，包括：位线和感测线; 数据存储元件，其具有根据施加到所述位线的电压而改变的数据存储状态; 用于控制感测线与位线的连接的第一开关; 数据锁存电路，具有第二数据保持节点和连接到感测线的第一数据保持节点; 以及用于控制数据锁存电路的第二数据保持节点与位线的连接的第二开关。