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    Smart handling of input/output interrupts
    51.
    发明授权
    Smart handling of input/output interrupts 有权

    公开(公告)号：US10078611B1

    公开(公告)日：2018-09-18

    申请号：US15626544

    申请日：2017-06-19

    申请人： QUALCOMM Incorporated

    发明人： Surendra Paravada ,  Madhu Yashwanth Boenapalli ,  Venu Madhav Mokkapati

    IPC分类号： G06F13/24 ,  G06F13/40 ,  G06F13/28 ,  G06F13/20

    CPC分类号： G06F13/409 ,  G06F13/20 ,  G06F13/28

    摘要： Aspects include computing devices and methods implemented by computing devices for smart of handling input/output interrupts associated with device setting levels. Various aspects may include receiving a hardware input/output interrupt from a hardware interface, updating an adjusted feature setting level, determining whether the adjusted feature setting level equals a feature setting level limit, and changing an interrupt service routine address stored at a first location of a hardware input/output register corresponding with an interrupt service routine associated with the hardware input/output interrupt to a first data in response to determining that the adjusted feature setting level of the computing device equals the adjusted feature setting level limit.

    Method and apparatus of real-time retimer delay measurement
    54.
    发明授权
    Method and apparatus of real-time retimer delay measurement 有权

    公开(公告)号：US10019385B2

    公开(公告)日：2018-07-10

    申请号：US15196889

    申请日：2016-06-29

    申请人： INTEL CORPORATION

    发明人： Huimin Chen

    IPC分类号： G06F13/10 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42

    CPC分类号： G06F13/102 ,  G06F13/16 ,  G06F13/20 ,  G06F13/4282 ,  G06F2213/0042

    摘要： Described is an apparatus comprising a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may be an elastic buffer coupled to a received clock, a local clock, a received-clock data, and a local-clock data. The second circuitry may assert a first flag when a set of values on the received-clock data matches part of a skip ordered set. The third circuitry may assert a second flag when a set of values on the local-clock data matches part of the skip ordered set. The fourth circuitry may increment a count value upon assertion of the first flag and may stop incrementing the count value upon assertion of the second flag. In some embodiments, additional circuitries may extract a first timestamp from a packet, sum the first timestamp and the count value, and substitute the sum for the first timestamp within the packet.

    INTEGRATED CIRCUIT INPUTS AND OUTPUTS
    56.
    发明申请
    INTEGRATED CIRCUIT INPUTS AND OUTPUTS 审中-公开

    公开(公告)号：US20180189210A1

    公开(公告)日：2018-07-05

    申请号：US15736762

    申请日：2016-06-16

    申请人： Nordic Semiconductor ASA

    发明人： Rolf AMBÜHL

    IPC分类号： G06F13/26 ,  H01L23/00

    CPC分类号： G06F13/26 ,  G06F13/20 ,  H01L24/18 ,  H01L2924/1432

    摘要： An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output subsystem (2) having at least one external connection (4). The external connection is configured to provide an input to or output from the device depending upon an associated setting in the general purpose input or output subsystem. At least one further module on the device is configured to be able to request at least a first or a second task which may control a state of the external connection, the general purpose input or output subsystem being configured, upon receipt of conflicting requests for the first and second tasks, to apply a predetermined priority to allow only one of the tasks to be applied to the external connection.