公开(公告)号：US11592884B2

公开(公告)日：2023-02-28

申请号：US16648206

申请日：2018-01-25

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Chia-Hung Kuo ,  Nivedita Aggarwal ,  Venkataramani Gopalakrishnan ,  Robert Gough ,  Basavaraj Astekar ,  Vijaykumar Kadgi

IPC: G06F1/26 ,  G06F1/3293 ,  G06F9/4401 ,  G06F13/42

Abstract: Apparatus and methods for managing power consumption of a data-path in a computer system are provided, the data-path comprising a first port and a second port, the first port comprising a high-speed and the second port comprising a low-speed port. The disclosed method including connecting a device to the data-path, determining that the connected device is to communicate using the second port and turning off an active circuit associated with the first port of the data-path.

公开(公告)号：US20220262427A1

公开(公告)日：2022-08-18

申请号：US17178015

申请日：2021-02-17

Applicant: Intel Corporation

Inventor： Nivedha Krishnakumar ,  Virendra Vikramsinh Adsure ,  Jaya Jeyaseelan ,  Nadav Bonen ,  Barnes Cooper ,  Toby Opferman ,  Vijay Bahirji ,  Chia-Hung Kuo

IPC: G11C11/406 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/402

Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

公开(公告)号：US20190041970A1

公开(公告)日：2019-02-07

申请号：US16142320

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Vijay S. R. Degalahal ,  Pronay Dutta ,  Robert Gough ,  Panner Kumar ,  Chia-Hung Kuo ,  Karthi Vadivelu

IPC: G06F1/32 ,  G06F9/4401

Abstract: In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

公开(公告)号：US10078608B2

公开(公告)日：2018-09-18

申请号：US15278128

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Vijaykumar B. Kadgi ,  Tin-Cheung Kung ,  Nivedita Aggarwal ,  Chia-Hung Kuo ,  Prashant Sethi

IPC: G06F13/38 ,  G06F13/20 ,  G06F9/44 ,  G06F11/30 ,  G06F9/4401

CPC classification number: G06F13/385 ,  G06F1/1632 ,  G06F1/263 ,  G06F1/266 ,  G06F9/4411 ,  G06F11/3051 ,  G06F13/20 ,  G06F2213/0042

Abstract: Various techniques for enabling the control and monitoring of a USB device mode controller to a USB-C connector, for the performance of a USB device mode data connection, are disclosed herein. In an example, a computing system that includes multiple USB-C connectors but a single USB device mode controller may manage the mapping of the controller to a particular connector, through operations that identify the mapping and the characteristics of the connector, process a request to change the mapping of the device mode controller, and perform the change to the mapping of the device mode controller. Such a change may include a disconnection or reassignment of a particular USB-C connector to the controller. Further examples to determine the availability of a USB device mode controller, and respond to a scenario where the USB device mode controller is not available, are also disclosed.

公开(公告)号：US11093020B2

公开(公告)日：2021-08-17

申请号：US15819552

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Vijaykumar B. Kadgi ,  Barnes Cooper ,  Nivedita Aggarwal ,  Venkataramani Gopalakrishnan ,  Jenn Chuan Cheng ,  Basavaraj Astekar ,  Charuhasini Sunderraman ,  Han Kung Chua ,  Anil Baby ,  Tin-Cheung Kung ,  Chia-Hung Kuo

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/42 ,  G06F13/38 ,  G06F1/26

Abstract: Techniques are provided for managing power delivery to multiple universal serial bus (USB) type-C ports of a desktop computer system. In an example, a method can include providing a first power level to a USB power delivery controller during a non-sleep mode operation of the desktop computer, and providing a second power level to the USB power delivery controller when the computer is in a sleep mode, the second power level configured to provide default charge power to a connected device when the computer is in the sleep mode.

公开(公告)号：US10998774B2

公开(公告)日：2021-05-04

申请号：US16085942

申请日：2016-07-21

Applicant: INTEL CORPORATION

Inventor： Hong W. Wong ,  Timothy Nguyen ,  Shaorong Zhou ,  Xiaoguo Liang ,  Chia-Hung Kuo

IPC: H02J50/80 ,  H02J50/90 ,  H02J50/05 ,  H02J50/10 ,  H02J7/00 ,  H01F38/14 ,  H02J7/02 ,  H05K7/20

Abstract: In one example a docking mat for an electronic device comprises a first major surface on which the electronic device may be positioned, a wireless power transmitting device, and a controller comprising logic, at least partly including hardware logic, to determine a location of the electronic device on the first major surface of the docking mat, establish a communication connection with the electronic device, receive at least one charge parameter from the electronic device, and activate the wireless power transmitting device in response to a determination that the electronic device is positioned proximate the wireless power transmitting device and the at least one charge parameter indicates that the electronic device is in a condition to receive power from the wireless power transmitting device. Other examples may be described.

公开(公告)号：US10831658B2

公开(公告)日：2020-11-10

申请号：US16239455

申请日：2019-01-03

Applicant: INTEL CORPORATION

Inventor： Yanru Li ,  Chia-Hung Kuo ,  Ali Taha

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0853 ,  G06F12/126 ,  G06F12/0811 ,  G06F12/0868

Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

公开(公告)号：US20170351502A1

公开(公告)日：2017-12-07

申请号：US15209476

申请日：2016-07-13

Applicant: Intel Corporation

Inventor： Nivedita Aggarwal ,  Reuven Rozic ,  Amir Levy ,  Chia-Hung Kuo

IPC: G06F9/445 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F9/4411

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate communication with electronic devices supported by an interface specification and electronic devices unsupported by the interface specification. An example apparatus includes a first firmware interface to facilitate communication between an operating system and a first electronic device, the first electronic device supported in an interface specification. The example apparatus includes a second firmware interface instantiated to facilitate communication with a second electronic device that is not supported in the interface specification, the second firmware interface configured to communicate with the first firmware interface to route communication between the operating system and the second electronic device via the first firmware interface and the second firmware interface.

公开(公告)号：US12165686B2

公开(公告)日：2024-12-10

申请号：US17178015

申请日：2021-02-17

Applicant: Intel Corporation

Inventor： Nivedha Krishnakumar ,  Virendra Vikramsinh Adsure ,  Jaya Jeyaseelan ,  Nadav Bonen ,  Barnes Cooper ,  Toby Opferman ,  Vijay Bahirji ,  Chia-Hung Kuo

IPC: G11C11/406 ,  G11C5/14 ,  G11C11/402 ,  G11C11/4074

Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

公开(公告)号：US20220197519A1

公开(公告)日：2022-06-23

申请号：US17128072

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Chia-Hung Kuo ,  Anoop Mukker ,  Eng Hun Ooi ,  Avishay Snir ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Wai Ben Lin

IPC: G06F3/06

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.