公开(公告)号：US10884483B2

公开(公告)日：2021-01-05

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US10860083B2

公开(公告)日：2020-12-08

申请号：US16142320

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Vijay S. R. Degalahal ,  Pronay Dutta ,  Robert Gough ,  Panner Kumar ,  Chia-Hung Kuo ,  Karthi Vadivelu

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3234 ,  G06F9/4401

Abstract: In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

公开(公告)号：US20190041970A1

公开(公告)日：2019-02-07

申请号：US16142320

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Vijay S. R. Degalahal ,  Pronay Dutta ,  Robert Gough ,  Panner Kumar ,  Chia-Hung Kuo ,  Karthi Vadivelu

IPC: G06F1/32 ,  G06F9/4401

Abstract: In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

公开(公告)号：US20190011976A1

公开(公告)日：2019-01-10

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/32

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.