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公开(公告)号：US20200287551A1
公开(公告)日：2020-09-10
申请号：US16291286
申请日：2019-03-04
Applicant: Xilinx, Inc.
Inventor： Mayank Raj , Didem Z. Turker Melek , Parag Upadhyaya , Yohan Frans , Kun-Yung Chang
Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.
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公开(公告)号：US10715358B1
公开(公告)日：2020-07-14
申请号：US16205020
申请日：2018-11-29
Applicant: Xilinx, Inc.
Inventor： Wenfeng Zhang , Stanley Y. Chen , Hsung Jai Im , Parag Upadhyaya
IPC: H04L25/03
Abstract: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.
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公开(公告)号：US10348310B1
公开(公告)日：2019-07-09
申请号：US15992646
申请日：2018-05-30
Applicant: Xilinx, Inc.
Inventor： Karim M. Megawer , Parag Upadhyaya , Didem Z. Turker Melek , Zhaoyin D. Wu
Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.
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公开(公告)号：US20180076134A1
公开(公告)日：2018-03-15
申请号：US15267035
申请日：2016-09-15
Applicant: Xilinx, Inc.
Inventor： Jing Jing , Shuxian Wu , Xin X. Wu , Parag Upadhyaya
IPC: H01L23/522 , H01L49/02 , H01L21/768 , H01L23/64
CPC classification number: H01L23/5227 , H01L23/5225 , H01L23/645 , H01L28/10
Abstract: A semiconductor device includes an interconnect structure disposed over a semiconductor substrate. The interconnect structure includes a first device disposed in a first portion of the interconnect structure. A first shielding plane including a first conductive material is disposed in a second portion of the interconnect structure over the first portion of the interconnect structure. A second device is disposed in a third portion of the interconnect structure over the second portion of the interconnect structure. An isolation wall including a second conductive material is disposed in the first, second, and third portions of the interconnect structure. The isolation wall is coupled to the first shielding plane, and surrounds the first device, the first shielding plane, and the second device.
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公开(公告)号：US09906232B1
公开(公告)日：2018-02-27
申请号：US15455915
申请日：2017-03-10
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Parag Upadhyaya , Chi Fung Poon
CPC classification number: H04L7/0087 , H03M1/007 , H03M1/40 , H03M1/462 , H04B1/0014 , H04L27/0002
Abstract: An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit configured to receive an analog input signal; a digital-to-analog converter (DAC); an adder having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit coupled to an output of the adder and configured to perform a comparison operation; and a control circuit, coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.
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Patent Agency Ranking
公开(公告)号：US20180013435A1
公开(公告)日：2018-01-11
申请号：US15206634
申请日：2016-07-11
Applicant: Xilinx, Inc.
Inventor： Jinyung Namkoong , Mayank Raj , Parag Upadhyaya , Vamshi Manthena , Catherine Hearne , Marc Erett
CPC classification number: H03L7/0891 , H03L7/0805 , H03L7/0995 , H03L7/24 , H03M9/00
Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.
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公开(公告)号：US09608611B1
公开(公告)日：2017-03-28
申请号：US15009462
申请日：2016-01-28
Applicant: Xilinx, Inc.
Inventor： Catherine Hearne , Parag Upadhyaya , Kevin Geary
CPC classification number: H03K5/135 , H03K2005/00052 , H03K2005/00058
Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.
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公开(公告)号：US09356556B1
公开(公告)日：2016-05-31
申请号：US14819764
申请日：2015-08-06
Applicant: Xilinx, Inc.
Inventor： Mayank Raj , Parag Upadhyaya
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03B27/00 , H03B2200/0048 , H03B2200/0078
Abstract: A circuit for implementing a dual-mode oscillator is disclosed. The circuit comprises a first oscillator portion having a first inductor coupled in parallel with a first capacitor between a first node and a second node; a first pair of output nodes coupled to the first and second nodes; a second oscillator portion inductively coupled to the first oscillator portion, the second oscillator portion having a second inductor coupled in parallel with a second capacitor between a third node and a fourth node; a second pair of output nodes coupled to the third and fourth nodes; and a control circuit coupled to enable a supply of current to either the first oscillator portion or the second oscillator portion. A method of implementing a dual-mode oscillator is also disclosed.
Abstract translation: 公开了一种用于实现双模振荡器的电路。 该电路包括第一振荡器部分，其具有与第一节点和第二节点之间的第一电容器并联耦合的第一电感器; 耦合到第一和第二节点的第一对输出节点; 电感耦合到第一振荡器部分的第二振荡器部分，第二振荡器部分具有与第三节点和第四节点之间的第二电容器并联耦合的第二电感器; 耦合到第三和第四节点的第二对输出节点; 以及控制电路，其被耦合以使得能够向第一振荡器部分或第二振荡器部分提供电流。 还公开了实现双模振荡器的方法。
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公开(公告)号：US09325277B1
公开(公告)日：2016-04-26
申请号：US14571805
申请日：2014-12-16
Applicant: Xilinx, Inc.
Inventor： Adebabay M. Bekele , Parag Upadhyaya
IPC: H03B5/12
CPC classification number: H03B5/1253 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1271 , H03B5/1278 , H03B5/129 , H03B2201/0208 , H03B2201/0266 , H03B2201/0291 , H03B2201/031 , H03B2201/038
Abstract: Voltage-controlled oscillation is described. In an apparatus therefor, an inductor has a tap and has or is coupled to a positive-side output node and a negative side output node. The tap is coupled to receive a first current. A coarse grain capacitor array is coupled to the positive-side output node and the negative side output node and is coupled to respectively receive select signals. A varactor is coupled to the positive-side output node and the negative side output node and is coupled to receive a control voltage. The varactor includes MuGFETs. A transconductance cell is coupled to the positive-side output node and the negative side output node, and the transconductance cell has a common node. A frequency scaled resistor network is coupled to the common node and is coupled to receive the select signals for a resistance for a path for a second current.
Abstract translation: 描述了压控振荡。 在其装置中，电感器具有抽头并且具有或耦合到正侧输出节点和负侧输出节点。 抽头被耦合以接收第一电流。 粗粒电容器阵列耦合到正侧输出节点和负侧输出节点，并被耦合以分别接收选择信号。 变容二极管耦合到正侧输出节点和负侧输出节点，并耦合以接收控制电压。 变异反应器包括MuGFETs。 跨导单元耦合到正侧输出节点和负侧输出节点，并且跨导单元具有公共节点。 频率比例电阻网络耦合到公共节点，并被耦合以接收用于第二电流的路径的电阻的选择信号。
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公开(公告)号：US08860180B2
公开(公告)日：2014-10-14
申请号：US13661195
申请日：2012-10-26
Applicant: Xilinx, Inc.
Inventor： Jing Jing , Shuxian Wu , Parag Upadhyaya
IPC: H01F5/04
CPC classification number: H01L28/10 , H01F17/0013 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.
Abstract translation: 在半导体集成电路内实现的电感器结构包括包括至少一个匝的导电材料的线圈和包围线圈的电流返回。 电流返回由半导体集成电路的多个互连的金属层形成。
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