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公开(公告)号：US06246422B1
公开(公告)日：2001-06-12
申请号：US09144863
申请日：1998-09-01
IPC分类号： G06T1140
CPC分类号： G06F12/0607 , G06T15/04
摘要： A method for storing mip map series in a multi-bank texture memory is disclosed. Each mip map has a different size and represents a different resolution version of a texture map image that is to be mapped onto a three dimensional object comprising one or more polygons. To prevent page faults when accessing corresponding texels in consecutive mip maps, each mip map is divided in two halves. The halves are stored in different banks of the multi-bank texture memory. The banks used are alternated so that corresponding texels in consecutive mip maps are stored in different memory banks. Mip maps may be categorized as large or small, with all small mip maps after the first being stored in their entirety in one memory bank. Small mip maps are those that are equal to or smaller than the page size of the multi-bank texture memory. A computer system, graphics subsystem, and software program capable to efficiently store mip map series in a multi-bank texture memories are also disclosed.
摘要翻译： 公开了一种在多组织纹理存储器中存储mip映射序列的方法。 每个mip映射具有不同的大小，并且表示要映射到包括一个或多个多边形的三维对象的纹理映射图像的不同分辨率版本。 为了防止在连续的mip地图访问相应的纹素时出现页面错误，每个mip映射被分成两半。 一半存储在多银行纹理存储器的不同库中。 使用的存储体是交替的，使得连续mip映射中的相应纹素被存储在不同的存储体中。 Mip地图可能被分类为大或小，所有小的mip地图首先被全部存储在一个存储器中。 小的mip映射是等于或小于多存储库纹理存储器的页面大小的映射。 还公开了能够有效地将mip映射序列存储在多存储体纹理存储器中的计算机系统，图形子系统和软件程序。
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52.发明授权
公开(公告)号：US6141741A
公开(公告)日：2000-10-31
申请号：US705057
申请日：1996-08-29
申请人： Curtis Priem , Satyanarayana Nishtala , Michael G. Lavelle , Thomas Webber , Daniel E. Lenoski , Peter A. Mehring , Guy Moffat , Christopher R. Owen
发明人： Curtis Priem , Satyanarayana Nishtala , Michael G. Lavelle , Thomas Webber , Daniel E. Lenoski , Peter A. Mehring , Guy Moffat , Christopher R. Owen
CPC分类号： G06F12/0215 , G06F13/161 , G06F13/1615
摘要： A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes. This overlapping operation allows the bus to be completely utilized during write operations, thereby improving data bandwidth.
摘要翻译： 描述了由系统存储器和从设备共享的具有多路复用地址总线的计算机系统。 通过提供总线控制器来在多路复用地址总线上执行两周期地址序列，将从设备并入现有系统存储器配置。 地址序列之后是数据传输。 在接收地址信息的时间和接收与地址信息对应的数据的时间之间可以存在随机延迟。 这个随机延迟可以被系统CPU用于其他计算目的。 在接收到第一个数据写入的确认之前，系统的总线控制器在总线上执行多个或流水线的数据写入。 在该方案中，通常在接收后续数据写入的相同时间段期间发送对第一数据写入的确认。 因此，数据传输确认与数据写入重叠。 这种重叠操作允许在写入操作期间完全利用总线，从而提高数据带宽。
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53.发明授权
公开(公告)号：US5963200A
公开(公告)日：1999-10-05
申请号：US914973
申请日：1997-08-20
IPC分类号： G06F3/153 , G06F3/14 , G09G5/00 , G09G5/06 , G09G5/08 , G09G5/12 , G09G5/18 , G09G5/397 , G09G5/399 , H04N13/00
CPC分类号： G06F3/1446 , G09G5/06 , G09G5/08 , G09G5/12 , G09G5/18 , H04N13/0048 , H04N13/0051 , H04N13/0497 , G06F3/1454 , G09G2310/0224 , G09G2360/04 , H04N13/0055 , H04N13/0429
摘要： A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master's FIELD signal. When they detect the master's FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.
摘要翻译： 用于同步可能存在于同一计算机上的多个帧缓冲器的垂直消隐的方法和装置，或者用于包括需要这种同步的立体显示，虚拟现实和视频记录的某些应用的单独的计算机。 为了获得所需的同步，一帧缓冲器被指定为主机。 它提供一个称为FIELD的信号，它在主帧缓冲区上的每个垂直同步事件的开始处改变状态（0到1或1到0）。 所有其他帧缓冲区都被设置为从站。 他们的定时发生器对主站的FIELD信号进行采样。 当他们检测到主站的FIELD信号改变状态时，它们设置自己的内部时序来匹配，从而实现帧同步。
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公开(公告)号：US5956046A
公开(公告)日：1999-09-21
申请号：US992196
申请日：1997-12-17
CPC分类号： G06F3/1438 , G09G5/12 , G09G5/399
摘要： A multi-display video system for ensuring the proper synchronization of scene switching. Before each display switches to pixel data corresponding to the next scene to be rendered, new pixel data is written into a currently unused bank of frame buffer memory within a corresponding graphics accelerator. When each graphics accelerator in the video system has completed writing the new pixel data to its respective frame buffer, the scene switch may take place. Each graphics accelerator is configured to display an image corresponding to the next scene in response to the indicator output signal indicating that the pixel data updates for all graphics accelerators are complete.
摘要翻译： 一种多显示视频系统，用于确保场景切换的正确同步。 在每个显示器切换到与要渲染的下一个场景相对应的像素数据之前，新的像素数据被写入相应图形加速器内的当前未使用的帧缓冲存储器组。 当视频系统中的每个图形加速器已经完成将新的像素数据写入其相应的帧缓冲器时，可能发生场景切换。 每个图形加速器被配置为响应于指示输出信号指示所有图形加速器的像素数据更新完成而显示对应于下一个场景的图像。
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公开(公告)号：US5544306A
公开(公告)日：1996-08-06
申请号：US237307
申请日：1994-05-03
CPC分类号： G09G5/39 , G06T15/405 , G06F12/0875 , G09G2340/10 , G09G2360/121 , G09G2360/123 , G09G2360/126
摘要： A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
摘要翻译： 公开了一种帧缓冲器动态随机存取存储器（FBRAM），其实现了Z缓冲图形基元的加速渲染。 FBRAM将读取 - 修改 - 写入事务（如Z缓冲区比较和RBG alpha混合）转换为只写操作。 FBRAM还实现了两级内部像素高速缓存和四路交错帧缓冲器。
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公开(公告)号：US08593468B2
公开(公告)日：2013-11-26
申请号：US12898249
申请日：2010-10-05
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
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57.发明申请公开(公告)号：US20080148063A1
公开(公告)日：2008-06-19
申请号：US10679055
申请日：2003-10-03
IPC分类号： G06F12/14
CPC分类号： H04N5/913 , G06F21/10 , G06F21/85 , G11B20/00086 , G11B20/0021 , H04L63/0464 , H04L63/0823 , H04L63/0869 , H04L2463/101 , H04N7/088 , H04N7/1675 , H04N21/2541 , H04N21/4334 , H04N21/4367 , H04N21/4405 , H04N21/4408 , H04N21/4627 , H04N21/835
摘要： In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.
摘要翻译： 在一类实施例中，本发明是其中嵌入了受保护的封闭子系统的开放式计算系统（例如，PC）。 封闭的子系统通常包括多个部分，确保内容保护密钥和受保护内容永远不会在封闭子系统外部显示。 进入封闭子系统（并且通常在封闭子系统内被解密并重新加密）的内容（例如，高清数字视频）在独立的封闭系统中可获得与开放系统相似的保护水平。 本发明的其他方面是用于保护开放式计算系统内的内容的方法，被配置为嵌入在开放式计算系统中的封闭系统（或其盘驱动器）以及被配置为嵌入开放式计算系统中的组合的输出的方法， 具有开放式计算系统的其他输出（例如，图形和/或音频输出）的封闭子系统。
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公开(公告)号：US06999087B2
公开(公告)日：2006-02-14
申请号：US10383165
申请日：2003-03-06
IPC分类号： G06F12/02
CPC分类号： G06T15/005 , G09G5/006 , G09G5/363 , G09G5/397 , G09G2340/0442 , G09G2340/0464 , G09G2360/08 , G09G2360/18
摘要： A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.
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59.发明授权公开(公告)号：US06975322B2
公开(公告)日：2005-12-13
申请号：US10383234
申请日：2003-03-06
申请人： Michael G. Lavelle
发明人： Michael G. Lavelle
CPC分类号： G06T15/005
摘要： A graphics system includes a hardware accelerator and a frame buffer. The frame buffer includes a sample storage area and a double-buffered display pixel area. The hardware accelerator is operable to (a) render a stream of primitives into samples, (b) store the samples into the sample storage area of the frame buffer, (c) read the samples from the sample storage area, (d) filter the samples to generate pixels, and (e) store the pixels into a first buffer of the display pixel area of the frame buffer. Furthermore, the hardware accelerator is operable to perform (a), (b), (c), (d) and (e) one or more times on one or more corresponding streams of primitives to complete a frame of an animation before passing control of the first buffer to a video output processor.
摘要翻译： 图形系统包括硬件加速器和帧缓冲器。 帧缓冲器包括样本存储区域和双缓冲显示像素区域。 硬件加速器可操作以（a）将原始流渲染为样本，（b）将样本存储到帧缓冲器的样本存储区域中，（c）从样本存储区域读取样本，（d）过滤 用于生成像素的样本，以及（e）将像素存储到帧缓冲器的显示像素区域的第一缓冲器中。 此外，硬件加速器可操作地在一个或多个相应的图元流上执行（a），（b），（c），（d）和（e）一次或多次以在通过控制之前完成动画的帧 的第一个缓冲区到视频输出处理器。
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60.发明授权Graphics primitive size estimation and subdivision for use with a texture accumulation buffer 有权用于纹理累积缓冲区的图形原始尺寸估计和细分公开(公告)号：US06914610B2
公开(公告)日：2005-07-05
申请号：US09861192
申请日：2001-05-18
申请人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
发明人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
摘要： A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.
摘要翻译： 图形系统被配置为将多层纹理信息应用于原语。 图形系统接收定义原语的参数，并对原语进行大小测试。 如果大小测试不能保证原语的片段大小小于或等于纹理累加缓冲区的片段容量，则将原语划分为子标识符，并且图形系统将多层纹理应用于与 原始。 当图形系统将与当前层对应的纹理应用于与图元相交的所有片段时，图形系统将从当前图层切换到该图层。 图形系统在连续纹理层的应用之间存储与纹理累积缓冲器中的原始片段相关联的颜色值。
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