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公开(公告)号：US06999087B2
公开(公告)日：2006-02-14
申请号：US10383165
申请日：2003-03-06
IPC分类号： G06F12/02
CPC分类号： G06T15/005 , G09G5/006 , G09G5/363 , G09G5/397 , G09G2340/0442 , G09G2340/0464 , G09G2360/08 , G09G2360/18
摘要： A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.
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公开(公告)号：US06784881B2
公开(公告)日：2004-08-31
申请号：US10037410
申请日：2002-01-04
申请人： Michael A. Wasserman , Michael G. Lavelle , Justin Michael Mahan , David Naegle , Glenn J. Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , Justin Michael Mahan , David Naegle , Glenn J. Gracon
IPC分类号： G09G500
CPC分类号： G06F3/1431 , G09G5/12 , G09G5/363
摘要： A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.
摘要翻译： 被配置为将从属显示通道同步到主显示通道的图形系统可以包括被配置为提供帧事件指示和从属显示定时发生器的主显示定时发生器。 从显示定时发生器可以被配置为接收帧事件指示，并且响应于在其有效显示周期期间接收帧事件指示，从属显示定时发生器可以被配置为等待直到其当前活动显示周期结束然后跳转 到其同步点。 或者，从显示定时发生器可以被配置为立即或在当前水平行的结束之后跳转到其同步点，并且可以在下一活动显示周期期间显示中断帧中的任何剩余显示信息。
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公开(公告)号：US08411096B1
公开(公告)日：2013-04-02
申请号：US11893503
申请日：2007-08-15
CPC分类号： G06T15/005 , G06F9/3881
摘要： Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. Several of these embodiments utilize offset registers associated with the instruction tables for the modules within the pipeline. The offset register serves as a pointer to locations in the instruction table, which allows instructions to be written to be instruction table, without requiring that the shader programs have explicit addresses. One embodiment describes a method of programming a graphics pipeline. This method involves accessing the shader program stored in memory. A shader instruction is generated from this shader program, and loaded into an instruction table associated with a target module graphics pipeline. The shader instruction is loaded into the instruction table at the location indicated by an offset register.
摘要翻译： 本文详细描述了用于编程图形管线和图形流水线内的模块的实施例。 这些实施例中的几个使用与管线内的模块的指令表相关联的偏移寄存器。 偏移寄存器用作指向指令表中的位置的指针，其允许将指令写入指令表，而不要求着色器程序具有显式地址。 一个实施例描述了编程图形流水线的方法。 该方法涉及访问存储在内存中的着色程序。 着色器指令从该着色器程序生成，并加载到与目标模块图形管道相关联的指令表中。 着色器指令在偏移寄存器指示的位置加载到指令表中。
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公开(公告)号：US09035957B1
公开(公告)日：2015-05-19
申请号：US11893443
申请日：2007-08-15
CPC分类号： G06F11/34 , G06F11/3024 , G06F11/3089 , G06F11/3409 , G06F11/3452 , G06F11/3476 , G06T1/20
摘要： An efficient pipeline debug statistics system and method are described. In one embodiment, an efficient pipeline debug is utilized in a graphics processing pipeline of a handheld device. In one embodiment, a pipeline debug statistics system includes a plurality of pipeline stages with probe points, a central statistic component, and a debug control component. The plurality of pipeline stages with probe points perform pipeline operations. The central statistic block gathers information from the probe points. The debug control component directs the gathering of information from the probe points. In one exemplary implementation, debug control component can direct gathering of information at a variety of levels and abstraction.
摘要翻译： 描述了一种高效的管道调试统计系统和方法。 在一个实施例中，在手持设备的图形处理流水线中利用有效的流水线调试。 在一个实施例中，管道调试统计系统包括具有探测点的多个流水线阶段，中央统计组件和调试控制组件。 具有探测点的多个流水线阶段执行管道操作。 中心统计块从探测点收集信息。 调试控制组件指导从探测点收集信息。 在一个示例性实现中，调试控制组件可以直接收集各种级别和抽象的信息。
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公开(公告)号：US09024957B1
公开(公告)日：2015-05-05
申请号：US11893427
申请日：2007-08-15
CPC分类号： G06F8/61 , G06F9/44557 , G06T15/005
摘要： A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.
摘要翻译： 将着色器程序从系统内存加载到GPU内存的方法。 该方法包括访问计算机系统的系统存储器中的着色器程序。 着色器程序从系统内存到GPU存储器的DMA传输被执行，使得着色器程序以独占于地址的方式被加载到GPU存储器中。
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公开(公告)号：US08780128B2
公开(公告)日：2014-07-15
申请号：US12002641
申请日：2007-12-17
CPC分类号： G06F12/0886 , G06F12/04 , G06T1/60
摘要： Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.
摘要翻译： 可以将数据元素（例如，像素）的数据存储在可寻址存储单元中，该存储单元可以存储不是每个数据元素的数据位数的整数倍的位数。 类似地，可以通过总线上的每单位时间传送多个数据元素，其中总线的宽度不是每个数据元素的数据位数的整数倍。 没有数据元素的数据存储在多个存储单元中或以多于一个单位的时间传输。 此外，用于多个数据元素的数据被连续地封装在存储单元中或跨越总线的宽度。
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公开(公告)号：US08736624B1
公开(公告)日：2014-05-27
申请号：US11893514
申请日：2007-08-15
CPC分类号： G06T15/005
摘要： Detailed herein are approaches to enabling conditional execution of instructions in a graphics pipeline. In one embodiment, a method of conditional execution controller operation is detailed. The method involves configuring the conditional execution controller to evaluate conditional test. A pixel data packet is received into the conditional execution controller, and evaluated, with reference to the conditional test. A conditional execution flag, associated with the pixel data packet, is set, to indicate whether a conditional operation should be performed on the pixel data packet.
摘要翻译： 这里详细描述了使图形管线中的指令能够进行条件执行的方法。 在一个实施例中，详细描述了一种条件执行控制器操作的方法。 该方法包括配置条件执行控制器以评估条件测试。 像素数据包被接收到条件执行控制器中，并参照条件测试进行评估。 设置与像素数据包相关联的条件执行标志，以指示是否应对像素数据包执行条件操作。
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公开(公告)号：US08698819B1
公开(公告)日：2014-04-15
申请号：US11893439
申请日：2007-08-15
CPC分类号： G06T1/20
摘要： Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. One embodiment described a method of implementing software assisted shader merging for a graphics pipeline. The method involves accessing a first shader program in memory, and generating a first shader instruction from that program. This first instruction is loaded into an instruction table at a first location, indicated by an offset register. A second shader program in memory is then accessed, and used to generate a second shader instruction. The second shader instruction is loaded into the instruction table at a second location indicated by the offset register.
摘要翻译： 本文详细描述了用于编程图形管线和图形流水线内的模块的实施例。 一个实施例描述了为图形管线实现软件辅助着色器合并的方法。 该方法涉及访问存储器中的第一着色器程序，并从该程序生成第一着色器指令。 该第一指令被加载到由偏移寄存器指示的第一位置的指令表中。 然后访问存储器中的第二个着色器程序，并用于生成第二个着色器指令。 第二个着色器指令在由偏移寄存器指示的第二个位置加载到指令表中。
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9.发明授权Program sequencer for generating indeterminant length shader programs for a graphics processor 有权用于为图形处理器生成不确定长度着色器程序的程序定序器公开(公告)号：US08659601B1
公开(公告)日：2014-02-25
申请号：US11893404
申请日：2007-08-15
CPC分类号： G06T15/005 , G06F9/5083 , G06T1/20
摘要： A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.
摘要翻译： 一种用于加载和执行不确定长度着色器程序的方法。 该方法包括访问GPU的图形存储器中的着色器程序的第一部分，并且将指令从第一部分加载到GPU的多个阶段以配置GPU用于程序执行。 然后根据来自第一部分的指令对一组像素进行处理。 在GPU的图形存储器中访问着色器程序的第二部分，并且来自第二部分的指令被加载到GPU的多个级中以配置GPU用于程序执行。 然后根据来自第二部分的指令对像素组进行处理。
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公开(公告)号：US20090157963A1
公开(公告)日：2009-06-18
申请号：US12002641
申请日：2007-12-17
CPC分类号： G06F12/0886 , G06F12/04 , G06T1/60
摘要： Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.
摘要翻译： 可以将数据元素（例如，像素）的数据存储在可寻址存储单元中，该存储单元可以存储不是每个数据元素的数据位数的整数倍的位数。 类似地，可以通过总线上的每单位时间传送多个数据元素，其中总线的宽度不是每个数据元素的数据位数的整数倍。 没有数据元素的数据存储在多个存储单元中或以多于一个单位的时间传输。 此外，用于多个数据元素的数据被连续地封装在存储单元中或跨越总线的宽度。
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