公开(公告)号：US10763260B2

公开(公告)日：2020-09-01

申请号：US16216954

申请日：2018-12-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/108 ,  H01L29/78 ,  H01L21/3105

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

公开(公告)号：US20190393080A1

公开(公告)日：2019-12-26

申请号：US16553202

申请日：2019-08-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Hsin-Yu Chiang ,  Yu-Ching Chen

IPC: H01L21/768 ,  H01L21/311

Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.

公开(公告)号：US20190181141A1

公开(公告)日：2019-06-13

申请号：US16175851

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench

公开(公告)号：US10290638B1

公开(公告)日：2019-05-14

申请号：US15964089

申请日：2018-04-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Tsun-Min Cheng ,  Shih-Fang Tzou ,  Chih-Chieh Tsai ,  Kai-Jiun Chang

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/10 ,  H01L21/306

Abstract: A method of forming dynamic random access memory (DRAM) device, comprises the following steps. First of all, a plurality of active areas is formed in a substrate along a first direction. Next, a plurality of buried gates disposed in the substrate is formed along a second trench extending along a second direction across the first direction. Then, a plurality of bit lines is formed over the buried gates and extended along a third direction across the first direction and the second direction, wherein each of the bit lines comprises a polysilicon layer, a barrier layer and a metal layer and the barrier layer is formed through a radio frequency physical vapor deposition (RF-PVD) process.

公开(公告)号：US20190081048A1

公开(公告)日：2019-03-14

申请号：US16036908

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L29/423 ,  H01L23/535

Abstract: A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.

公开(公告)号：US20190080961A1

公开(公告)日：2019-03-14

申请号：US16188237

申请日：2018-11-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/108 ,  H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate is provided and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

公开(公告)号：US20190067293A1

公开(公告)日：2019-02-28

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US20180323190A1

公开(公告)日：2018-11-08

申请号：US15610642

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Shih-Fang Tzou

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66666

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US20180254277A1

公开(公告)日：2018-09-06

申请号：US15894947

申请日：2018-02-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ching Chen ,  Shih-Fang Tzou ,  Kuei-Hsuan Yu ,  Hui-Ling Chuang

IPC: H01L27/108

CPC classification number: H01L27/10847 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.

公开(公告)号：US20180240705A1

公开(公告)日：2018-08-23

申请号：US15472295

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L21/76895 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/528 ,  H01L23/535 ,  H01L27/10888 ,  H01L29/0649

Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.