公开(公告)号：US20150028423A1

公开(公告)日：2015-01-29

申请号：US14513807

申请日：2014-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US08796127B2

公开(公告)日：2014-08-05

申请号：US13734306

申请日：2013-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeseok Kim ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。

公开(公告)号：US20130237045A1

公开(公告)日：2013-09-12

申请号：US13734306

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeseok KIM ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。