公开(公告)号：US09153603B2

公开(公告)日：2015-10-06

申请号：US14105048

申请日：2013-12-12

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Young Park ,  Dong Il Kim ,  Sang Gab Kim

IPC: H01L21/00 ,  H01L27/12

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1248 ,  H01L27/1259

Abstract: A thin film transistor array panel includes a substrate; a gate line located over the substrate and including a gate pad portion; a data line located over the gate line and including a source electrode and a data pad portion; a drain electrode; a first passivation layer located over the data line and the drain electrode; an organic insulating layer located over the first passivation layer and having a contact hole; a first field generating electrode located over the organic insulating layer and having an opening; a second passivation layer located over the first field generating electrode; and a second field generating electrode located over the second passivation layer. The contact hole coincides with or is smaller than the opening, and the contact hole has a tapered structure.

Abstract translation: 薄膜晶体管阵列面板包括基板; 栅极线，位于衬底上并包括栅极焊盘部分; 位于栅极线上方并包括源电极和数据焊盘部分的数据线; 漏电极; 位于数据线和漏电极之上的第一钝化层; 位于所述第一钝化层上并具有接触孔的有机绝缘层; 位于所述有机绝缘层上方并具有开口的第一场产生电极; 位于第一场产生电极之上的第二钝化层; 以及位于第二钝化层上方的第二场产生电极。 接触孔与开口重合或小于开口，接触孔具有锥形结构。

公开(公告)号：US08853703B2

公开(公告)日：2014-10-07

申请号：US13830269

申请日：2013-03-14

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

IPC: H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/062 ,  H01L31/113 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

公开(公告)号：US20140175441A1

公开(公告)日：2014-06-26

申请号：US13927781

申请日：2013-06-26

Applicant: Samsung Display Co., Ltd.

Inventor： Hong-Kee CHIN ,  Yun Jong Yeo ,  Sang Gab Kim ,  Jung-Suk Bang ,  Byeong Hoon Cho

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1218 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1446 ,  H01L31/03765 ,  H01L31/1136 ,  H01L31/204

Abstract: A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion. The first semiconductor is disposed on the insulation layer. The second semiconductor is disposed on the insulation layer and includes a semiconductor material different than the first semiconductor. The stepped portion is spaced apart from an edge of the first semiconductor.

Abstract translation: 薄膜晶体管阵列面板包括基板，绝缘层，第一半导体和第二半导体。 绝缘层设置在基板上并且包括台阶部分。 第一半导体设置在绝缘层上。 第二半导体设置在绝缘层上，并且包括与第一半导体不同的半导体材料。 台阶部分与第一半导体的边缘间隔开。

公开(公告)号：US20140167040A1

公开(公告)日：2014-06-19

申请号：US14184361

申请日：2014-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。