公开(公告)号：US20150279454A1

公开(公告)日：2015-10-01

申请号：US14658163

申请日：2015-03-14

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract translation: 提供的半导体存储装置可以增加写入裕度并抑制芯片面积的增加。 半导体存储装置包括以矩阵形式布置的多个存储单元; 对应于存储器单元的每列布置的多个位线对; 写入驱动器电路，根据写入数据将数据发送到所选列的位线对; 以及将所选列的位线对的低电位侧的位线驱动到负电压电平的写辅助电路。 写辅助电路包括第一信号线; 第一驱动电路，其根据控制信号驱动第一信号布线; 以及第二信号布线，其通过与第一信号布线的线间耦合电容通过第一驱动电路的驱动而耦合到低电位侧的位线并产生负电压。

公开(公告)号：US20150078058A1

公开(公告)日：2015-03-19

申请号：US14454357

申请日：2014-08-07

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: G11C11/412 ,  G11C5/06 ,  G11C11/418 ,  G11C8/12 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C29/1201 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/1104 ,  H01L27/1116

Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.

Abstract translation: 提供一种半导体存储装置，包括：第一存储单元; 第一个字线 第一位线 第一个通用位线; 第二存储单元; 第二个字线 第二位线 第二个通用位线; 第一选择电路，其将第一公共位线连接到从第一位线选择的第一位线; 第二选择电路，其将所述第二公共位线连接到从所述第二位线选择的第二位线; 字线驱动器，其激活第一和第二字线中的任何一个; 参考电流供应单元，其将第一和第二公共位线之间的公共位线提供参考电流，所述公共位线未电连接到数据读取目标存储器单元; 以及放大第一和第二公共位线之间的电位差的读出放大器。

公开(公告)号：US20150029784A1

公开(公告)日：2015-01-29

申请号：US14334790

申请日：2014-07-18

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Hidehiro FUJIWARA

IPC: G11C11/41

CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Abstract translation: 提供了一种半导体集成电路器件，其可以抑制开销来产生唯一的ID。 当产生唯一的ID时，SRAM中的存储单元的字线的电位升高到高于SRAM的电源电压，然后降低到SRAM的电源电压以下。 当字线的电位高于SRAM的电源电压时，相同的数据被提供给存储单元的两个位线。 由此，SRAM中的存储单元处于未定义状态，然后变化，以便根据构成存储单元的元件等的特性保持数据。 在SRAM的制造中，存在构成存储单元的元件等的特性的变化。 因此，SRAM中的存储单元根据制造中发生的变化来保存数据。

公开(公告)号：US20140070212A1

公开(公告)日：2014-03-13

申请号：US14022721

申请日：2013-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

IPC: G06K19/07

CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏; 被配置为存储测试地址的测试地址存储单元; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。