公开(公告)号：US11089325B2

公开(公告)日：2021-08-10

申请号：US16783697

申请日：2020-02-06

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/55

Abstract: An example device for coding video data may include a memory configured to store a current block of the video data and one or more processors implemented in circuitry coupled to the memory. The one or more processor may be configured to determine delta motion vectors from control point motion vectors of a neighboring block of a current block. The one or more processors may also be configured to clip the delta motion vectors to a predefined range. The one or more processors may also be configured to code the current block of video data using the clipped delta motion vectors.

公开(公告)号：US20210160535A1

公开(公告)日：2021-05-27

申请号：US16952736

申请日：2020-11-19

Applicant: QUALCOMM Incorporated

Inventor： Chun-Chi Chen ,  Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/513 ,  H04N19/52 ,  H04N19/577 ,  H04N19/176

Abstract: A video coder is configured to determine bi-directional motion vectors of a current block of the video data and determine that a condition is satisfied with respect to the current block based on each component of the bi-directional motion vectors of the current block being less than a threshold value. The video coder is further configured to, based on the condition being satisfied with respect to the current block, early terminate application of a motion vector refinement process to the bi-directional motion vectors of the current block. The video coder is further configured to determine a prediction block for the current block based on the bi-directional motion vectors of the current block and reconstruct the current block based on the prediction block for the current block.

公开(公告)号：US10958932B2

公开(公告)日：2021-03-23

申请号：US16566571

申请日：2019-09-10

Applicant: QUALCOMM Incorporated

Inventor： Wei-Jung Chien ,  Yu Han ,  Han Huang ,  Marta Karczewicz

IPC: H04N11/02 ,  H04N19/52 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176

Abstract: An example device for coding video data includes a processor configured to construct a motion vector predictor list for a current block of video data. The processor adds motion vectors for a first set of blocks that immediately neighbor the current block to the motion vector predictor list. The processor determines whether motion vectors for a second set of blocks that are separated from the current block by one or more blocks are duplicates of motion vectors in the motion vector predictor list, and if not, adds the motion vectors to the motion vector predictor list. The processor inter prediction codes the current block with a motion vector and codes the motion vector using the motion vector predictor list. The processor may further use a temporal motion vector as a motion vector predictor for the motion vector.

公开(公告)号：US20210044828A1

公开(公告)日：2021-02-11

申请号：US16947489

申请日：2020-08-04

Applicant: QUALCOMM Incorporated

Inventor： Luong Pham Van ,  Han Huang ,  Geert Van der Auwera ,  Adarsh Krishnan Ramasubramonian ,  Cheng-Teh Hsieh ,  Wei-Jung Chien ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/593 ,  H04N19/176 ,  H04N19/186 ,  H04N19/96

Abstract: A video decoder can be configured to determine that a block of the video data is formatted in accordance with a 4:4:4 video coding format; determine that the block of the video data is encoded in an intra prediction mode; determine that a smallest chroma intra prediction unit (SCIPU) is disabled for the block in response to determining that the block has the 4:4:4 video coding format; decode the block of the video data based on the determination that the SCIPU is disabled; and output decoded video data comprising a decoded version of the block.

公开(公告)号：US20200374550A1

公开(公告)日：2020-11-26

申请号：US16858046

申请日：2020-04-24

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/577 ,  H04N19/176 ,  H04N19/159 ,  H04N19/169

Abstract: A video coder is configured to code a block of video data using bi-prediction with bi-directional optical flow. The video coder may determine an offset using bi-directional optical flow and may add the offset to prediction samples determined from the bi-prediction. In one example, the video coder code a current block of video data using bi-prediction and bi-directional optical flow, wherein the bi-directional flow does not include one or more of a rounding operation or a division by 2 in an offset calculation. Additionally, the video coder may perform a motion vector refinement calculation for the bi-directional flow, wherein the motion vector refinement calculation is compensated to account for the offset calculation not including the division by 2.

公开(公告)号：US20200314419A1

公开(公告)日：2020-10-01

申请号：US16829626

申请日：2020-03-25

Applicant: QUALCOMM Incorporated

Inventor： Hongtao Wang ,  Han Huang ,  Yu Han ,  Geert Van der Auwera ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/11 ,  H04N19/139 ,  H04N19/132 ,  H04N19/159 ,  H04N19/70 ,  H04N19/186 ,  H04N19/176

Abstract: A video coder selects a set of wide-angle intra prediction directions based on a size of a luma block of a picture having a YUV 4:2:2 chroma sampling format. Additionally, the video coder determines an intra prediction direction for the luma block. The intra prediction direction for the luma block is in the set of wide-angle intra prediction directions. The video coder also determines an intra prediction direction for a chroma block. The luma block is collocated in the picture with the chroma block. The chroma block has a different width/height ratio than the luma block. The intra prediction direction for the chroma block is guaranteed to have the intra prediction direction for the luma block. The video coder uses the intra prediction directions for the luma and chroma blocks to generate prediction blocks for the luma and chroma blocks, respectively.

公开(公告)号：US20200288156A1

公开(公告)日：2020-09-10

申请号：US16802352

申请日：2020-02-26

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/44 ,  H04N19/137 ,  H04N19/119 ,  H04N19/159 ,  H04N19/176

Abstract: A video encoder and/or video decoder may determine the size of subblocks of a block of video data, where the block of video data is to be encoded or decoded using subblock affine motion compensation mode. The video encoder and/or video decoder may receive a block of video data to be coded using a subblock affine motion compensation mode, determine a size of one or more subblocks of the block based on one or more of an inter prediction direction or affine motion parameters of the block, partition the block into the one or more subblocks based on the determined size, and code the one or more subblocks using the subblock affine motion compensation mode.

公开(公告)号：US20200186807A1

公开(公告)日：2020-06-11

申请号：US16705016

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Vadim Seregin ,  Wei-Jung Chien ,  Han Huang ,  Marta Karczewicz

IPC: H04N19/14 ,  H04N19/105 ,  H04N19/119 ,  H04N19/423 ,  H04N19/176

Abstract: A video coder can be configured to code video data by determining a first block size threshold for a block of video data; determining a second block size threshold, wherein the second block size threshold is smaller than the first block size threshold; partitioning the block of video data into smaller sub-blocks; in response to determining that a first partition of the partitioned block is smaller or equal to the first block size threshold, determining that blocks within the partition belong to a parallel estimation area; and in response to determining that a second partition of the partitioned block is smaller or equal to the second block size threshold, determining that blocks within the second partition belong to an area for a shared candidate list.

公开(公告)号：US20200021839A1

公开(公告)日：2020-01-16

申请号：US16506720

申请日：2019-07-09

Applicant: QUALCOMM Incorporated

Inventor： Luong Pham Van ,  Wei-Jung Chien ,  Vadim Seregin ,  Marta Karczewicz ,  Han Huang

IPC: H04N19/52 ,  H04N19/513 ,  H04N19/615 ,  H04N19/15

Abstract: An example device for coding video data includes a memory configured to store video data; and one or more processing units implemented in circuitry and configured to: store motion information for a first coding tree unit (CTU) line of a picture in a first history motion vector predictor (MVP) buffer of the memory; reset a second history MVP buffer of the memory; and after resetting the second history MVP buffer, store motion information for a second CTU line of the picture in the second history MVP buffer, the second CTU line being different than the first CTU line. Separate threads of a video coding process executed by the one or more processors may process respective CTU lines, in some examples.

公开(公告)号：US20250119527A1

公开(公告)日：2025-04-10

申请号：US18882225

申请日：2024-09-11

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Vadim Seregin ,  Hongtao Wang ,  Zhi Zhang ,  Chun-Chi Chen ,  Han Huang ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/157 ,  H04N19/176 ,  H04N19/52 ,  H04N19/70

Abstract: Example devices, methods, and computer-readable media are disclosed for decoding video data. An example method includes determining to decode a current block of the video data using a merge mode. The example method includes obtaining a flag from a bitstream. The example method includes determining, based on a value of the flag, to use a second merge list of two merge lists for the current block, wherein the second merge list is based on a first merge list of the two merge lists. The example method includes decoding the current block based on the second merge list.