公开(公告)号：US11652156B2

公开(公告)日：2023-05-16

申请号：US17506742

申请日：2021-10-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Juntao Li ,  Dechao Guo ,  Tao Li ,  Tsung-Sheng Kang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/785

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

公开(公告)号：US20230054701A1

公开(公告)日：2023-02-23

申请号：US17406351

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  JUNTAO LI ,  Carl Radens

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.

公开(公告)号：US20220399491A1

公开(公告)日：2022-12-15

申请号：US17346686

申请日：2021-06-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

公开(公告)号：US20220246739A1

公开(公告)日：2022-08-04

申请号：US17719682

申请日：2022-04-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Veeraraghavan S. Basker ,  Juntao Li

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/40

Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

公开(公告)号：US10833204B2

公开(公告)日：2020-11-10

申请号：US16591873

申请日：2019-10-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

公开(公告)号：US10832916B1

公开(公告)日：2020-11-10

申请号：US16511640

申请日：2019-07-15

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Veeraraghavan S. Basker

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

公开(公告)号：US20200006561A1

公开(公告)日：2020-01-02

申请号：US16539294

申请日：2019-08-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  JUNLI WANG ,  Lawrence A. Clevenger ,  Carl Radens ,  John H. Zhang

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.

公开(公告)号：US10438850B1

公开(公告)日：2019-10-08

申请号：US16042585

申请日：2018-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/092 ,  H01L21/8238

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.

公开(公告)号：US10431495B1

公开(公告)日：2019-10-01

申请号：US16042561

申请日：2018-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A technique relates to a semiconductor device. A first trench silicide (TS) is coupled to a first source or drain (S/D). A second TS is coupled to a second S/D, and a gate metal is separated from the first and second TS. A trench is formed above and on sides of the gate metal. A local connection metal is formed in the trench such that the gate metal is coupled to the first TS and the second TS. A local connection cap is formed on top of the local connection metal.

公开(公告)号：US09905511B2

公开(公告)日：2018-02-27

申请号：US14937812

申请日：2015-11-10

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yiheng Xu ,  Lawrence A. Clevenger ,  Carl Radens ,  Edem Wornyo

IPC: H03H11/40 ,  H01L23/525 ,  H01L49/02 ,  H01F17/02 ,  H01L23/522 ,  H01F17/00

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.