公开(公告)号：US06340637B2

公开(公告)日：2002-01-22

申请号：US09730038

申请日：2000-12-05

申请人： Ravi Iyer ,  Sujit Sharan

发明人： Ravi Iyer ,  Sujit Sharan

IPC分类号： H01L2144

CPC分类号： C23C16/08 ,  H01L21/28556 ,  H01L21/28568 ,  Y10S438/909

摘要： A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5. The reaction gases for the improved process are titanium tetrachloride and a hydrocarbon gas, which for a preferred embodiment of the process is methane. The reaction is carried out in a plasma environment created by a radio frequency source greater than 10 KHz. The key to obtaining titanium metal as a reaction product, rather than titanium carbide, is to set the plasma sustaining electrical power within a range that will remove just one hydrogen atom from each molecule of the hydrocarbon gas. In a preferred embodiment of the process, highly reactive methyl radicals (CH3—) are formed from methane gas. These radicals attack the titanium-chlorine bonds of the tetrachloride molecule and form chloromethane, which is evacuated from the chamber as it is formed. Titanium metal deposits an a wafer or other substrate that has been heated to a temperature within a preferred range of 200-500° C.

摘要翻译： 公开了一种通过化学气相沉积沉积钛金属层的新工艺。 该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。 用于改进方法的反应气体是四氯化钛和烃气体，其中该方法的优选实施方案是甲烷。 该反应在由大于10KHz的射频源产生的等离子体环境中进行。 获得钛金属作为反应产物而不是碳化钛的关键是将等离子体维持电功率设置在仅从烃气体的每个分子除去一个氢原子的范围内。 在该方法的优选实施方案中，由甲烷气体形成高反应性甲基（CH 3 - ）。 这些自由基攻击四氯化碳分子的钛 - 氯键，并形成氯甲烷，其形成时从室中排出。 钛金属沉积了已被加热到200-500℃的优选范围内的晶片或其它基底。

公开(公告)号：US06333556B1

公开(公告)日：2001-12-25

申请号：US08947847

申请日：1997-10-09

申请人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC分类号： H01L23485

CPC分类号： H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

摘要翻译： 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06313046B1

公开(公告)日：2001-11-06

申请号：US09115339

申请日：1998-07-14

申请人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

摘要翻译： 本发明涵盖在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06277737B1

公开(公告)日：2001-08-21

申请号：US09146113

申请日：1998-09-02

申请人： Gurtej S. Sandhu ,  Ravi Iyer

发明人： Gurtej S. Sandhu ,  Ravi Iyer

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685

摘要： In aspect, the invention includes a semiconductor processing method comprising: a) forming an electrically insulative layer over a substrate; b) forming an opening within the electrically insulative layer, the opening having a periphery defined at least in part by a bottom surface and a sidewall surface; c) forming a first layer comprising TiN within the opening, the first layer being over the bottom surface and along the sidewall surface; d) forming a second layer comprising elemental Ti over the electrically insulative layer but substantially not within the opening, the second layer having a thickness of less than 50 Å along the sidewall surface and over the bottom surface; and e) forming an aluminum-comprising layer within the opening and over the second layer. In another aspect, the invention includes a semiconductor processing method comprising: a) forming a first aluminum-comprising layer over an electrically insulative layer; b) forming a first titanium-comprising layer over the first aluminum-comprising layer; c) forming a second titanium-comprising layer over the first titanium-comprising layer, one of the first and second titanium-comprising layers comprising elemental Ti and the other of the first and second titanium-comprising layers comprising TiN; and d) forming a second aluminum-comprising layer over the second titanium-comprising layer.

摘要翻译： 在本发明中，本发明包括半导体处理方法，包括：a）在衬底上形成电绝缘层; b）在所述电绝缘层内形成开口，所述开口具有至少部分地由底表面和侧壁表面限定的周边; c）在所述开口内形成包含TiN的第一层，所述第一层在所述底表面上并沿着所述侧壁表面; d）在所述电绝缘层上形成包括元素Ti的第二层，但基本上不在所述开口内，所述第二层沿着所述侧壁表面并在所述底表面上具有小于的厚度; 以及e）在所述开口内和所述第二层上形成含铝层。 另一方面，本发明包括一种半导体处理方法，包括：a）在电绝缘层上形成第一含铝层; b）在所述第一含铝层上形成第一含钛层; c）在所述第一含钛层上形成第二含钛层，所述第一和第二含钛层中的一个包含元素Ti，所述第一和第二含钛层中的另一个包含TiN; 以及d）在所述第二含钛层上形成第二含铝层。

公开(公告)号：US06204175B1

公开(公告)日：2001-03-20

申请号：US09226053

申请日：1999-01-05

申请人： Gilbert Lai ,  Gurtej S. Sandhu ,  Ravi Iyer ,  Brian A. Vaartstra

发明人： Gilbert Lai ,  Gurtej S. Sandhu ,  Ravi Iyer ,  Brian A. Vaartstra

IPC分类号： H01L2144

CPC分类号： H01L21/28568 ,  C23C16/0272 ,  C23C16/44 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76877

摘要： A method of forming a conformal aluminum film on a refractory metal nitride layer is provided and includes positioning a substrate having the refractory metal nitride layer thereon within a chemical vapor deposition chamber; establishing a nominal temperature for the substrate; introducing a carrier gas containing a gaseous, metalorganic precursor into the chamber for a time sufficient to form a metallic seed layer; and introducing a carrier gas containing a gaseous aluminum metalorganic precursor into the chamber for a time sufficient to form a conformal aluminum metal film over the metal refractory nitride layer.

摘要翻译： 提供了在难熔金属氮化物层上形成共形铝膜的方法，包括将其上具有难熔金属氮化物层的基板定位在化学气相沉积室内; 建立基板的标称温度; 将含有气态金属有机前体的载气引入室中足以形成金属种子层的时间; 并将含有气态铝金属有机前体的载气引入室中足以在金属耐火氮化物层上形成共形铝金属膜的时间。

公开(公告)号：US6162499A

公开(公告)日：2000-12-19

申请号：US144484

申请日：1998-08-31

申请人： Gurtej S. Sandhu ,  Ravi Iyer ,  Donald L. Westmoreland

发明人： Gurtej S. Sandhu ,  Ravi Iyer ,  Donald L. Westmoreland

IPC分类号： C23C16/44 ,  B05D7/22 ,  C23C16/00

CPC分类号： C23C16/4404

摘要： A method of inhibiting deposition of material on a wall of a chemical vapor deposition reactor includes providing a chemical vapor deposition reactor having a wall which has an inside facing surface, the inside facing surface at least partially defining a chemical vapor deposition reactor chamber; forming a first material atop the inside facing surface; positioning a substrate in the chemical vapor deposition a reactor chamber, the substrate having an outer surface; and chemical vapor depositing a second material layer on the substrate in a manner which is selective to the substrate outer surface, and not the first material, thereby restricting deposition of the second layer on the reactor inside facing surface.

摘要翻译： 一种抑制材料沉积在化学气相沉积反应器的壁上的方法包括提供具有壁的化学气相沉积反应器，所述壁具有面向内的表面，所述内表面至少部分地限定化学气相沉积反应室; 在面向内表面的顶部形成第一材料; 将基板定位在化学气相沉积中的反应室，所述基板具有外表面; 以及以对衬底外表面有选择性的方式在衬底上沉积第二材料层，而不是第一材料，由此限制第二层在反应器面对表面上的沉积。

公开(公告)号：US6156630A

公开(公告)日：2000-12-05

申请号：US916275

申请日：1997-08-22

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/76895

摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.

公开(公告)号：US6121133A

公开(公告)日：2000-09-19

申请号：US916276

申请日：1997-08-22

申请人： Ravi Iyer ,  Steven M. McDonald ,  Thomas R. Glass ,  Zhiping Yin

发明人： Ravi Iyer ,  Steven M. McDonald ,  Thomas R. Glass ,  Zhiping Yin

IPC分类号： G03F7/11 ,  G03F7/09 ,  H01L21/027 ,  H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L21/4763

CPC分类号： G03F7/091 ,  G03F7/092 ,  H01L21/0276 ,  H01L21/32 ,  H01L21/76202 ,  Y10T428/24471 ,  Y10T428/24917

摘要： A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

公开(公告)号：US6001541A

公开(公告)日：1999-12-14

申请号：US49970

申请日：1998-03-27

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76814 ,  H01L21/31144

摘要： The invention comprises methods of forming contact openings and methods of forming contacts. In but one implementation, an inorganic antireflective coating material layer is formed over an insulating material layer. A contact opening is etched through the inorganic antireflective coating layer and into the insulating layer. Insulative material within the contact opening is etched and a projection of inorganic antireflective coating material is formed within the contact opening. The inorganic antireflective coating material is etched to substantially remove the projection from the contact opening. The preferred etching to remove the projection is facet etching, most preferably plasma etching. The preferred inorganic antireflective coating material is selected from the group consisting of SiO.sub.x where "x" ranges from 0.1 to 1.8, SiN.sub.y where "y" ranges from 0.1 to 1.2, and SiO.sub.x N.sub.y where "x" ranges from 0.2 to 1.8 and "y" ranges from 0.01 to 1.0, and mixtures thereof. In another implementation, only a portion of the inorganic antireflective coating layer is removed from over the insulating material layer after initially etching the contact opening. After removing the portion of the inorganic antireflective coating layer, the insulating material layer is etched to widen at least a portion of the contact opening. The invention also contemplates use of organic antireflective coating layers.

摘要翻译： 本发明包括形成接触开口的方法和形成接触的方法。 但是在一个实施方式中，在绝缘材料层上形成无机抗反射涂层层。 通过无机抗反射涂层蚀刻接触开口并进入绝缘层。 蚀刻接触开口内的绝缘材料，并且在接触开口内形成无机抗反射涂层材料的突起。 对无机抗反射涂层材料进行蚀刻以基本上从接触开口移除突起。 去除突起的优选蚀刻是刻面蚀刻，最优选等离子体蚀刻。 优选的无机抗反射涂层材料选自SiO x，其中“x”为0.1至1.8，SiN y其中“y”为0.1至1.2，SiO x N y为“x”为0.2至1.8，“y” 范围为0.01至1.0，以及它们的混合物。 在另一个实施方案中，在最初蚀刻接触开口之后，仅在绝缘材料层上除去无机抗反射涂层的一部分。 在去除无机抗反射涂层的部分之后，绝缘材料层被蚀刻以加宽接触开口的至少一部分。 本发明还考虑使用有机抗反射涂层。

公开(公告)号：US5981380A

公开(公告)日：1999-11-09

申请号：US27537

申请日：1998-02-23

申请人： Jigish D. Trivedi ,  Ravi Iyer

发明人： Jigish D. Trivedi ,  Ravi Iyer

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/45 ,  H01L21/70

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002

摘要： A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.