公开(公告)号：US20130264632A1

公开(公告)日：2013-10-10

申请号：US13812070

申请日：2012-04-24

Applicant: Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

Inventor： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/66742 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: The invention relates to a thin film transistor memory and its fabricating method, This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulting layer and the second layer metal nanocrystals grown by ALD method. in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown. by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method. The TFT memory in this invention has the advantage with large P/E window, good data retention, high P/E speed, stable threshold voltage and simple fabricating process.

Abstract translation: 本发明涉及薄膜晶体管存储器及其制造方法，从底部到顶部使用基板作为栅电极的存储器包括电荷阻挡层，电荷存储层，电荷隧道层，器件的有源区和 源/漏电极。 电荷阻挡层是ALD生长的Al 2 O 3膜。 电荷存储层是由ALD法生长的第一层金属纳米晶体，绝缘层和第二层金属纳米晶体的两层金属纳米晶体。 从下到上。 电荷隧道层是包括生长的SiO 2 / HfO 2 / SiO 2或Al 2 O 3 / HfO 2 / Al 2 O 3膜的对称堆叠层。 通过ALD方法从下到上依次。 器件的有源区是通过RF溅射法生长的IGZO膜，并且通过标准光刻和湿蚀刻法形成。 本发明的TFT存储器具有P / E窗口大，数据保持性好，P / E速度高，阈值电压稳定，制造工艺简单的优点。

公开(公告)号：US20130237010A1

公开(公告)日：2013-09-12

申请号：US13554531

申请日：2012-07-20

Applicant: Pengfei Wang ,  Xi Lin ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Xi Lin ,  Qingqing Sun ,  Wei Zhang

IPC: H01L21/336 ,  H01L21/36

CPC classification number: H01L21/8258 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate.

Abstract translation: 本发明属于半导体器件制造技术领域，具体公开了一种栅控二极管半导体存储器件的制造方法。 本发明通过低温工艺制造栅极控制二极管半导体存储器件，其特征在于制造具有高驱动电流和小次阈值摆幅的栅极控制二极管存储器件的简单工艺，低制造成本和容量。 本发明提出的用于制造栅极控制二极管半导体存储器件的方法特别适用于基于柔性基板的平板显示器和相变存储器以及存储器件的制造。

公开(公告)号：US20130187278A1

公开(公告)日：2013-07-25

申请号：US13381182

申请日：2011-04-08

Applicant: Pengfei Wang ,  Wei Zhang

Inventor： Pengfei Wang ,  Wei Zhang

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/7682 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention belongs to the technical field of semiconductor devices, and discloses a structure for interconnecting a medium of low dielectric constant with copper and the integration method thereof. It includes: using a combination of copper interconnections and air gaps to reduce capacity, and a special structure to support copper conductors so as to maintain the shape of copper conductors after removing the medium. The advantage of the present invention is that it can realize the complete air gap structure without short circuit or disconnection of copper conductors as well as the complete air gap structure with long conductors, thus reducing RC delay.

Abstract translation: 本发明属于半导体器件的技术领域，并且公开了一种用于将低介电常数与铜相互连接的结构及其集成方法。 它包括：使用铜互连和气隙的组合来降低容量，以及支持铜导体的特殊结构，以便在去除介质之后保持铜导体的形状。 本发明的优点是可以实现完整的气隙结构，而且铜导体的短路或断开以及具有长导体的完整气隙结构，从而减少RC延迟。

公开(公告)号：US08486754B1

公开(公告)日：2013-07-16

申请号：US13534983

申请日：2012-06-27

Applicant: Pengfei Wang ,  Chengwei Cao ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Chengwei Cao ,  Qingqing Sun ,  Wei Zhang

IPC: H01L21/00

CPC classification number: H01L29/22 ,  H01L29/66356 ,  H01L29/7391

Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.

Abstract translation: 本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体器件的方法。 当栅极电压相对较高时，栅极下方的沟道具有n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过栅极将n型ZnO转换成p型并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。 本发明特征在于能够通过高驱动电流和小的次阈值摆幅的优点来制造能够降低芯片功耗的栅极控制二极管器件的能力，特别适用于具有平板显示器的读写装置的制造， 相变存储器以及基于柔性基板的半导体器件。

公开(公告)号：US20120309118A1

公开(公告)日：2012-12-06

申请号：US13304149

申请日：2011-11-23

Applicant: Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

Inventor： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC: H01L21/66

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593

Abstract: A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.

Abstract translation: 公开了用于高完整性封装技术领域的硅通孔互连中使用的硅晶片对准方法。 在一个方面，该方法包括对准和校准上下硅晶片，电子层叠和互连，以提高硅晶片的对准精度并降低互连电阻。 在一些实施例中，通过该方法制造的集成电路芯片提高了速度和能量性能。

公开(公告)号：US20120305880A1

公开(公告)日：2012-12-06

申请号：US13457035

申请日：2012-04-26

Applicant: Wei Zhang ,  Lin Chen ,  Peng Zhou ,  Qingqing Sun ,  Pengfei Wang

Inventor： Wei Zhang ,  Lin Chen ,  Peng Zhou ,  Qingqing Sun ,  Pengfei Wang

IPC: H01L45/00

CPC classification number: G11C13/0007 ,  G11C2213/55 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable.

Abstract translation: 本发明属于存储器的技术领域，具体涉及一种具有电场强化层的电阻随机存取存储器结构及其制造方法。 本发明的电阻式随机存取存储器可以包括顶电极，底电极和复合层，它放置在顶电极和底电极之间，并具有第一电阻开关层和第二电阻开关和电场强化 层; 第二电阻开关和电场强化层驾驶室与第一电阻式开关层相邻，其介电常数低于第一电阻式开关层的介电常数。 RRAM单元中的电场分布是可调的。

公开(公告)号：US08101290B2

公开(公告)日：2012-01-24

申请号：US12252153

申请日：2008-10-15

Applicant: PengFei Wang ,  Na Li ,  Weimin Liu ,  Shuit-Tong Lee ,  Chun-Sing Lee

Inventor： PengFei Wang ,  Na Li ,  Weimin Liu ,  Shuit-Tong Lee ,  Chun-Sing Lee

IPC: H01L51/50 ,  C07D401/10 ,  C07D405/14 ,  H01J1/63

CPC classification number: C07D405/14 ,  C07D213/53 ,  C07D213/57 ,  C07D213/80 ,  C07D213/85 ,  H01L51/0067 ,  H01L51/5048 ,  H01L2251/308 ,  Y10S428/917

Abstract: Disclosed herein are several organic compounds having electron-transporting and/or hole-blocking performance and their preparation method and use and the OLEDs comprising the organic compound. The organic compounds exhibit high ionization potential (IP), electron affinity (Ea), glass transition temperature (Tg) and high electron mobility, and are a kind of good electron-transporting material with good hole-blocking ability. The devices comprising these compounds as one of the emitting layer, electron-transporting layer (ETL) and hole-blocking layer (HBL) show improved efficiency and better color purity.

Abstract translation: 本文公开了具有电子传输和/或空穴阻断性能的几种有机化合物及其制备方法和用途以及包含有机化合物的OLED。 有机化合物表现出高电离电位（IP），电子亲和力（Ea），玻璃化转变温度（Tg）和高电子迁移率，是一种具有良好的空穴阻挡能力的良好的电子传输材料。 包含这些化合物作为发光层，电子传输层（ETL）和空穴阻挡层（HBL）之一的器件显示出提高的效率和更好的色纯度。

公开(公告)号：US08048541B2

公开(公告)日：2011-11-01

申请号：US12336734

申请日：2008-12-17

Applicant: Shuit-Tong Lee ,  Chun Sing Lee ,  Pengfei Wang ,  Zhiyuan Xie

Inventor： Shuit-Tong Lee ,  Chun Sing Lee ,  Pengfei Wang ,  Zhiyuan Xie

IPC: H01L51/50

CPC classification number: C07D401/04 ,  C07D241/46 ,  C09K11/06 ,  C09K2211/1029 ,  C09K2211/1044 ,  H05B33/14

Abstract: An electroluminescence device has an anode, a cathode and an emitting layer located between the anode and the cathode. The emitting layer contains a compound selected from a group consisting of neutral red and its derivatives.

Abstract translation: 电致发光器件具有位于阳极和阴极之间的阳极，阴极和发射层。 发光层含有选自中性红及其衍生物的化合物。