公开(公告)号：US20140167134A1

公开(公告)日：2014-06-19

申请号：US13514032

申请日：2012-02-02

Applicant: Pengfei Wang ,  Xi Lin ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Xi Lin ,  Qingqing Sun ,  Wei Zhang

IPC: H01L27/115

CPC classification number: H01L27/11563 ,  G11C16/0475 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1026 ,  H01L27/1157 ,  H01L27/1203 ,  H01L29/7391 ,  H01L29/7923 ,  H01L29/8616

Abstract: The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density.

Abstract translation: 本发明属于半导体存储器件的技术领域，具体涉及一种自对准的垂直非易失性半导体存储器件，包括：半导体衬底，第一掺杂类型的漏极区域，第二掺杂型的两个源极区域， 用于捕获电子的堆叠栅; 其中漏极区域，两个源极区域和堆叠的栅极形成共享一个栅极和一个漏极的两个隧道场效应晶体管（TFET），每个TFET的漏极区域电流受到电荷的量和分布的影响 用于捕获电子的堆叠栅极，漏极埋在半导体衬底中，漏极区域上方的源极区域通过沟道与漏极分离，并通过第一掺杂类型的区域彼此分离。 本发明的半导体存储器件具有小的单位面积和简单的制造工艺。 使用本发明的存储芯片的制造成本低，存储密度高。

公开(公告)号：US20140034891A1

公开(公告)日：2014-02-06

申请号：US13376994

申请日：2011-08-15

Applicant: Pengfei Wang ,  Xi Lin ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Xi Lin ,  Qingqing Sun ,  Wei Zhang

IPC: H01L27/24

CPC classification number: H01L27/2463 ,  H01L27/2445 ,  H01L27/2472 ,  H01L29/7391 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675

Abstract: The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process.

Abstract translation: 本发明属于微电子器件的技术领域，具体涉及一种半导体存储器结构及其制造方法。 形成通过隧道场效应晶体管对相变存储器或电阻变化存储器进行擦除，写入和读取操作的半导体存储器结构，一方面，当电流通过隧道场效应晶体管时， pn结积极偏置，满足擦除和写入相变存储器和电阻变化存储器的高电流要求，另一方面，场效应晶体管的垂直结构可以大大提高存储器件阵列的密度 。 本发明还公开了一种非常适用于存储芯片的方法，用于使用自对准工艺制造半导体存储器结构。

公开(公告)号：US08574958B2

公开(公告)日：2013-11-05

申请号：US13535032

申请日：2012-06-27

Applicant: Pengfei Wang ,  Xiaoyong Liu ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Xiaoyong Liu ,  Qingqing Sun ,  Wei Zhang

IPC: H01L21/00

CPC classification number: H01L29/7391 ,  H01L29/8616

Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc.

Abstract translation: 本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。 当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，并配置了简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反转为p型，并使用NiO作为p型半导体，形成npnp掺杂结构， 浮动门中的电荷决定了器件的阈值电压，从而实现了存储器的功能。 本发明具有制造栅极控制二极管存储器件的能力，其能够通过高驱动电流和小的次级阈值摆动的优点来降低芯片功耗。 本发明适用于基于柔性基板和平板显示器和浮动栅极存储器等的半导体器件制造。

公开(公告)号：US20130178013A1

公开(公告)日：2013-07-11

申请号：US13534983

申请日：2012-06-27

Applicant: Pengfei Wang ,  Chengwei Cao ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Chengwei Cao ,  Qingqing Sun ,  Wei Zhang

IPC: H01L21/34

CPC classification number: H01L29/22 ,  H01L29/66356 ,  H01L29/7391

Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.

Abstract translation: 本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体器件的方法。 当栅极电压相对较高时，栅极下方的沟道具有n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过栅极将n型ZnO转换成p型并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。 本发明特征在于能够通过高驱动电流和小的次阈值摆幅的优点来制造能够降低芯片功耗的栅极控制二极管器件的能力，特别适用于具有平板显示器的读写装置的制造， 相变存储器以及基于柔性基板的半导体器件。

公开(公告)号：US20130149824A1

公开(公告)日：2013-06-13

申请号：US13537956

申请日：2012-06-29

Applicant: Pengfei Wang ,  Xi Lin ,  Wei Liu ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Xi Lin ,  Wei Liu ,  Qingqing Sun ,  Wei Zhang

IPC: H01L21/336

CPC classification number: H01L29/7391 ,  H01L29/0657 ,  H01L29/0895 ,  H01L29/517 ,  H01L29/66356

Abstract: The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.

Abstract translation: 本发明属于半导体器件制造的技术领域，具体涉及一种具有U形沟道的隧道效应晶体管的制造方法。 U型通道可以有效地延长晶体管沟道长度，抑制晶体管中漏电流的产生，降低芯片功耗。 本发明提出的具有U形通道的隧道场效应晶体管的制造方法能够实现非常窄的U形沟道，克服由光刻引入的取向偏差，提高芯片集成度。

公开(公告)号：US20130078761A1

公开(公告)日：2013-03-28

申请号：US13528462

申请日：2012-06-20

Applicant: Qingqing Sun ,  Runchen Fang ,  Wen Yang ,  Pengfei Wang ,  Wei Zhang

Inventor： Qingqing Sun ,  Runchen Fang ,  Wen Yang ,  Pengfei Wang ,  Wei Zhang

IPC: H01L21/336

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: The present invention belongs to the technical field of low temperature atomic layer deposition technology, and specifically relates to a method for manufacturing a flexible transparent 1T1R storage unit. In the present invention, a fully transparent 1T1R storage unit is developed on a flexible substrate through a completely low-temperature process, including an oxide layer dielectric, a transparent electrode and a transparent substrate which are deposited together through a low-temperature process, thus realizing a fully transparent device capable of achieving the functions of nontransparent devices. The present invention can be applied to the manufacturing of flexible low-temperature storage units in the future, as well as changing the packaging and existing modes of devices, which will make foldable and bendable portable storage units possible.

Abstract translation: 本发明属于低温原子层沉积技术的技术领域，具体涉及柔性透明1T1R存储单元的制造方法。 在本发明中，完全透明的1T1R存储单元通过完全低温处理在柔性基板上开发，包括通过低温工艺沉积在一起的氧化物层电介质，透明电极和透明衬底，因此 实现能够实现非透明设备功能的完全透明的设备。 本发明可以应用于将来的柔性低温存储单元的制造，以及改变装置的现有模式，这使得可折叠和可弯曲的便携式存储装置成为可能。

公开(公告)号：US09099178B2

公开(公告)日：2015-08-04

申请号：US13457035

申请日：2012-04-26

Applicant: Wei Zhang ,  Lin Chen ,  Peng Zhou ,  Qingqing Sun ,  Pengfei Wang

Inventor： Wei Zhang ,  Lin Chen ,  Peng Zhou ,  Qingqing Sun ,  Pengfei Wang

IPC: H01L29/86 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  G11C2213/55 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable.

Abstract translation: 本发明属于存储器的技术领域，具体涉及一种具有电场强化层的电阻随机存取存储器结构及其制造方法。 本发明的电阻式随机存取存储器可以包括顶电极，底电极和复合层，它放置在顶电极和底电极之间，并具有第一电阻开关层和第二电阻开关和电场强化 层; 第二电阻开关和电场强化层驾驶室与第一电阻式开关层相邻，其介电常数低于第一电阻式开关层的介电常数。 RRAM单元中的电场分布是可调的。

公开(公告)号：US08860179B2

公开(公告)日：2014-10-14

申请号：US13392208

申请日：2011-05-19

Applicant: Pengfei Wang ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Qingqing Sun ,  Wei Zhang

IPC: H01L27/00 ,  H01L23/522 ,  H01L23/64 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L22/14 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/13 ,  H01L24/94 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/32145 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00

Abstract: The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.

Abstract translation: 本发明公开了一种通过硅经由互连形成的电感元件。 通过使用硅通过技术的特殊硅通孔互连形成的电感元件具有诸如高电感和密度等优点。 此外，形成电感元件的贯通硅通孔互连集成工艺与普通的通过硅互连一体化工艺兼容，无任何其他步骤，从而使工艺简单稳定。 使用本发明的电感元件可应用于各种芯片的直通硅封装制造，特别是功率控制芯片和射频芯片的封装制造。

公开(公告)号：US20130078797A1

公开(公告)日：2013-03-28

申请号：US13528363

申请日：2012-06-20

Applicant: Qingqing Sun ,  Lin Chen ,  Wen Yang ,  Pengfei Wang ,  Wei Zhang

Inventor： Qingqing Sun ,  Lin Chen ,  Wen Yang ,  Pengfei Wang ,  Wei Zhang

IPC: H01L21/768

CPC classification number: H01L21/28562 ,  C23C16/18 ,  C23C16/45534 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability.

Abstract translation: 本发明属于集成半导体电路的技术领域，涉及铜扩散阻挡层的制造方法。 在本发明中，已经选择了适当的反应前体，并且已经采用原子层沉积（ALD）技术来在TaN层上形成Co或Ru，以获得在不超过32个工艺节点的互连中使用的扩散阻挡层 nm，克服了PVD沉积Ta / TaN双层结构作为铜扩散阻挡层在步骤覆盖和一致性方面的不足，并且有效地解决了Cu / low-k双镶嵌工艺中的各种严重问题，如 凹槽和通孔中的空隙的产生以及电迁移稳定性。

公开(公告)号：US20130056848A1

公开(公告)日：2013-03-07

申请号：US13392208

申请日：2011-05-19

Applicant: Pengfei Wang ,  Qingqing Sun ,  Wei Zhang

Inventor： Pengfei Wang ,  Qingqing Sun ,  Wei Zhang

IPC: H01L23/522

CPC classification number: H01L22/14 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/13 ,  H01L24/94 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/32145 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00

Abstract: The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.

Abstract translation: 本发明公开了一种通过硅经由互连形成的电感元件。 通过使用硅通过技术的特殊硅通孔互连形成的电感元件具有诸如高电感和密度等优点。 此外，形成电感元件的贯通硅通孔互连集成工艺与普通的通过硅互连一体化工艺兼容，无任何其他步骤，从而使工艺简单稳定。 使用本发明的电感元件可应用于各种芯片的直通硅封装制造，特别是功率控制芯片和射频芯片的封装制造。