公开(公告)号：US07442611B2

公开(公告)日：2008-10-28

申请号：US11657154

申请日：2007-01-24

Applicant: Victor W. C. Chan ,  Yong M. Lee ,  Haining Yang

Inventor： Victor W. C. Chan ,  Yong M. Lee ,  Haining Yang

IPC: H01L21/8234

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/665

Abstract: A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

Abstract translation: 提供了制造半导体器件结构的方法。 在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。 可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。 期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与 离子注入。 然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。 以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。 应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。

公开(公告)号：US20080251934A1

公开(公告)日：2008-10-16

申请号：US11734931

申请日：2007-04-13

Applicant: Jack Allan Mandelman ,  Haining Yang

Inventor： Jack Allan Mandelman ,  Haining Yang

IPC: H01L29/267 ,  H01L21/3205

CPC classification number: H01L27/11 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/1104

Abstract: Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.

Abstract translation: 用于制造用于静态随机存取存储器（SRAM）器件的这种半导体器件结构的半导体器件结构和方法。 半导体器件结构包括设置在第一和第二半导体区域之间的介质区域和在第一和第二半导体区域之间延伸的栅极导体结构。 栅极导体结构具有覆盖第一半导体区域的第一侧壁。 器件结构还包括延伸跨越第一半导体区域的电连接桥。 电连接桥具有将第一半导体区域中的杂质掺杂区域与栅极导体结构的第一侧壁电连接的部分。

公开(公告)号：US07436030B2

公开(公告)日：2008-10-14

申请号：US11463640

申请日：2006-08-10

Applicant: Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

Inventor： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract translation: 公开了一种在分离的硅层上并入应变MOSFET的IC的制造方法和结构。 N沟道场效应晶体管（nFET）和P沟道FET（pFET）分别形成在分离的硅层上。 因此，可以形成与nFET和pFET相邻的浅沟槽绝缘（STI）区域，以对各个nFET和pFET的沟道区域产生不同的应力。 因此，通过STI应力可以提高nFET和pFET两者的性能。 此外，当两个硅层相对于彼此垂直地定位时，IC的面积也可以减小。

公开(公告)号：US20080122110A1

公开(公告)日：2008-05-29

申请号：US11555801

申请日：2006-11-02

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor device including a contact region. The semiconductor structure also includes a passivation layer passivating the semiconductor device including the contact region. A narrow bottomed stepped sidewall contact aperture is located within the passivation layer to expose the contact region. A corresponding narrow bottomed stepped sidewall contact via is located within the narrow bottomed stepped sidewall contact aperture to contact the contact region. The narrow bottomed stepped sidewall contact aperture and contact via provide for improved contact to the contact region and reduced parasitic capacitance with respect to the semiconductor device. Methods for fabricating the narrow bottomed stepped sidewall contact aperture use a mask layer (either dimensionally diminished or dimensionally augmented) in conjunction with a two step etch method.

Abstract translation: 半导体结构包括包括接触区域的半导体器件。 半导体结构还包括钝化层，钝化包括接触区域的半导体器件。 窄的有底阶梯式侧壁接触孔位于钝化层内以暴露接触区域。 相应的窄底部阶梯状侧壁接触通孔位于窄底部阶梯状侧壁接触孔内，以接触接触区域。 窄的有底阶梯式侧壁接触孔和接触通孔提供与接触区域的改善的接触并减小相对于半导体器件的寄生电容。 制造窄底阶阶侧壁接触孔的方法结合两步蚀刻方法使用掩模层（尺寸减小或尺寸增大）。

公开(公告)号：US20080122026A1

公开(公告)日：2008-05-29

申请号：US11564344

申请日：2006-11-29

Applicant: Xiangdong Chen ,  Deok-Kee Kim ,  Haining Yang

Inventor： Xiangdong Chen ,  Deok-Kee Kim ,  Haining Yang

IPC: H01L29/00

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention is directed to an improved eFUSE that prevent rupturing of the fuse link, reduces current through the fuse link, and optimizes electromigration through the fuse link through the use of a feedback circuit.

Abstract translation: 本发明涉及一种改进的eFUSE，其防止熔丝链断裂，减少通过熔丝链的电流，并且通过使用反馈电路优化通过熔断体的电迁移。

公开(公告)号：US20080070357A1

公开(公告)日：2008-03-20

申请号：US11928976

申请日：2007-10-30

Applicant: Xiangdong Chen ,  Haining Yang

Inventor： Xiangdong Chen ,  Haining Yang

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

Abstract translation: 公开了包括PMOSFET和NMOSFETS的应变MOSFET的半导体结构以及制造应变MOSFET的方法，其优化MOSFET中的应变，并且更特别地使MOSFET的一种（P或N）中的应变最大化并且使 另一种（N或P）MOSFET的应变。 在PMOSFET和NMOSFET两者上形成具有原始全厚度的应变诱导性氮化碳氮化物涂层，其中应变诱导涂层在一种半导体器件中产生优化的全应变，并降低其他种类的半导体器件的性能。 诱导氮化钛涂层的应变被蚀刻到比另一种半导体器件更薄的厚度，其中应变诱导涂层的减小的厚度在其它MOSFET中松弛并产生较小的应变。

公开(公告)号：US20080036012A1

公开(公告)日：2008-02-14

申请号：US11463640

申请日：2006-08-10

Applicant: Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

Inventor： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

IPC: H01L29/76

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract translation: 公开了一种在分离的硅层上并入应变MOSFET的IC的制造方法和结构。 N沟道场效应晶体管（nFET）和P沟道FET（pFET）分别形成在分离的硅层上。 因此，可以形成与nFET和pFET相邻的浅沟槽绝缘（STI）区域，以对各个nFET和pFET的沟道区域产生不同的应力。 因此，通过STI应力可以提高nFET和pFET两者的性能。 此外，当两个硅层相对于彼此垂直地定位时，IC的面积也可以减小。

公开(公告)号：US20070298572A1

公开(公告)日：2007-12-27

申请号：US11850076

申请日：2007-09-05

Applicant: Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

Inventor： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L29/665 ,  H01L29/6659

Abstract: A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

Abstract translation: 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

公开(公告)号：US20070298552A1

公开(公告)日：2007-12-27

申请号：US11851464

申请日：2007-09-07

Applicant: Thomas Dyer ,  Haining Yang

Inventor： Thomas Dyer ,  Haining Yang

IPC: H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

Abstract translation: 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

公开(公告)号：US20070187773A1

公开(公告)日：2007-08-16

申请号：US11738883

申请日：2007-04-23

Applicant: Haining YANG ,  Huilong ZHU

Inventor： Haining YANG ,  Huilong ZHU

IPC: H01L29/94

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  Y10S257/90

Abstract: A semiconductor device is provided with a stressed channel region, where the stress film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surrounds the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

Abstract translation: 半导体器件设置有应力沟道区域，其中引起应力沟道区域中的应力的应力膜可以部分地或全部地在半导体器件的栅极结构下延伸。 在一些实施例中，应力膜环围绕通道区域，并且可以施加来自通道的所有侧面的应力。 因此，应力膜更好地围绕半导体器件的沟道区域并且可以在沟道区域中施加更多的应力。