公开(公告)号：US09735797B2

公开(公告)日：2017-08-15

申请号：US15360349

申请日：2016-11-23

申请人： ANALOG DEVICES, INC.

发明人： Jialin Zhao ,  Qingdong Meng ,  Yunzhi Dong ,  Jose Barreiro Silva

IPC分类号： H03M1/00 ,  H03M1/10 ,  H03M1/46 ,  H03M3/00

CPC分类号： H03M1/1071 ,  H03M1/1038 ,  H03M1/16 ,  H03M1/38 ,  H03M1/46 ,  H03M3/412 ,  H03M3/464

摘要： For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

公开(公告)号：US09621182B2

公开(公告)日：2017-04-11

申请号：US15027168

申请日：2014-10-02

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： David Lachartre

IPC分类号： H04B1/06 ,  H03M3/00 ,  H03M1/12 ,  H04B1/16 ,  H03M1/48

CPC分类号： H03M3/424 ,  H03M1/125 ,  H03M1/48 ,  H03M3/412 ,  H03M3/464 ,  H04B1/16

摘要： A device for quantizing an analog input signal, for supply of a continuous-time output signal quantized using a plurality of bits, includes a sign analysis electronic circuit, configured to supply a first signal representative of a first sign bit of the output signal, and an envelope analysis electronic circuit, including a comparator/quantizer with two inputs one of which receives the analog input signal, configured to supply a second signal representative of at least a second bit of the output signal, as a quantized envelope signal, and a feedback loop with continuous-time digital-to-analog conversion of the quantized envelope signal, arranged between the output and the other of the two inputs of the comparator/quantizer. The quantized envelope signal is a signal of which a low pass filtering is representative of the amplitude of an envelope signal of the input signal and the feedback loop includes a low pass filter.

公开(公告)号：US20160248438A1

公开(公告)日：2016-08-25

申请号：US15027168

申请日：2014-10-02

申请人： COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

发明人： David LACHARTRE

IPC分类号： H03M3/00 ,  H04B1/16

CPC分类号： H03M3/424 ,  H03M1/125 ,  H03M1/48 ,  H03M3/412 ,  H03M3/464 ,  H04B1/16

摘要： A device for quantizing an analog input signal, for supply of a continuous-time output signal quantized using a plurality of bits, includes a sign analysis electronic circuit, configured to supply a first signal representative of a first sign bit of the output signal, and an envelope analysis electronic circuit, including a comparator/quantizer with two inputs one of which receives the analog input signal, configured to supply a second signal representative of at least a second bit of the output signal, as a quantized envelope signal, and a feedback loop with continuous-time digital-to-analog conversion of the quantized envelope signal, arranged between the output and the other of the two inputs of the comparator/quantizer. The quantized envelope signal is a signal of which a low pass filtering is representative of the amplitude of an envelope signal of the input signal and the feedback loop includes a low pass filter.

摘要翻译： 用于量化模拟输入信号的装置，用于提供使用多个位量化的连续时间输出信号，包括符号分析电子电路，其被配置为提供表示输出信号的第一符号位的第一信号，以及 包络分析电子电路，包括具有两个输入的比较器/量化器，其中一个接收模拟输入信号，被配置为提供表示输出信号的至少第二位的第二信号作为量化包络信号，以及反馈 循环，其连续时间数字到模拟转换量化包络信号，布置在比较器/量化器的两个输入端之间的输出端和另一端之间。 量化包络信号是低通滤波表示输入信号的包络信号的幅度的信号，反馈回路包括低通滤波器。

公开(公告)号：US09246509B1

公开(公告)日：2016-01-26

申请号：US14474945

申请日：2014-09-02

申请人： STMicroelectronics Pvt. Ltd.

发明人： Neha Bhargava ,  Ankur Bal

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/412 ,  H03M1/145 ,  H03M1/68 ,  H03M3/382 ,  H03M3/424 ,  H03M3/458 ,  H03M3/464

摘要： A sigma delta analog-to-digital converter includes a sigma delta modulator including a segmented digital-to-analog converter (DAC), the segmented DAC including a coarse DAC and a fine DAC, wherein the sigma delta modulator is configured to generate a coarse quantized signal and a fine quantized signal; recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between the coarse DAC and the fine DAC of the segmented DAC.

摘要翻译： Σ-Δ模数转换器包括包括分段数模转换器（DAC）的Σ-Δ调制器，分段DAC包括粗DAC和精细DAC，其中，Σ-Δ调制器被配置为产生粗 量化信号和精细量化信号; 复合逻辑，被配置为组合所述粗量化信号和所述精细量化信号; 以及可在校准模式下操作的校准电路，以校准复合逻辑以补偿分段DAC的粗DAC和精细DAC之间的失配。

公开(公告)号：US08928511B2

公开(公告)日：2015-01-06

申请号：US13691860

申请日：2012-12-03

申请人： Mediatek Inc.

发明人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

IPC分类号： H03M3/00 ,  H03M7/30

CPC分类号： H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息。

公开(公告)号：US20140333462A1

公开(公告)日：2014-11-13

申请号：US14268409

申请日：2014-05-02

申请人： NXP B.V.

发明人： Lucien Johannes Breems

IPC分类号： H03M3/00

CPC分类号： H03M3/39 ,  H03M3/412 ,  H03M3/42 ,  H03M3/454

摘要： A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308′) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310′) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.

摘要翻译： 包括第一滤波器级（304）的Σ-Δ调制器（300） 与所述第一过滤器级（304）串联的第二过滤器级（306）; 在第二滤波器级（306）的输出与第二滤波级（306）的输入端之间的第一反馈路径（311），第一反馈（311）包括第一增益级（308,308'），使得 第一反馈路径（311）被配置为提供第一增益值; 以及在第二滤波器级（306）的输出与第一滤波级（304）的输入之间的第二反馈路径（313），第二反馈路径（313）包括第二增益级（309; 310'）， 第二反馈路径（313）被配置为提供第二增益值。 第一增益值与第二增益值不同。

公开(公告)号：US20120112943A1

公开(公告)日：2012-05-10

申请号：US13072797

申请日：2011-03-28

申请人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

发明人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

IPC分类号： H03M3/02

CPC分类号： H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.

摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

公开(公告)号：US07889108B2

公开(公告)日：2011-02-15

申请号：US12436813

申请日：2009-05-07

申请人： Koichi Hamashita ,  Gábor C Temes ,  Yan Wang

发明人： Koichi Hamashita ,  Gábor C Temes ,  Yan Wang

IPC分类号： H03M3/00

CPC分类号： H03M3/412 ,  H03M3/424 ,  H03M3/448 ,  H03M3/452 ,  H03M7/3028 ,  H03M7/304

摘要： A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.

摘要翻译： 公开了混合ΔΣADC结构和方法来实现具有单比特输出的高分辨率Δ-Σ调制器。 该系统包含一个低阶多位模拟噪声整形环路，其次是高阶单位数字调制器。 该组合简化了模拟调制器，并允许使用大多数满量程输入范围。

公开(公告)号：US07522079B1

公开(公告)日：2009-04-21

申请号：US11850960

申请日：2007-09-06

申请人： Jian-Yi Wu

发明人： Jian-Yi Wu

IPC分类号： H03M3/00

CPC分类号： H03M3/412 ,  H03M3/454 ,  H03M3/464

摘要： A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator, and further providing increased tolerance of non-ideal integrators.

摘要翻译： Σ-Δ调制器具有反馈数模转换器，其具有比量化器更低的分辨率，同时提供减小长度的输出字，需要最小额外的内部处理，并通过有效噪声传递函数对截断误差进行整形 比主机Σ-Δ调制器的顺序，并且进一步提供非理想积分器的增加的容限。

公开(公告)号：US20080062026A1

公开(公告)日：2008-03-13

申请号：US11531144

申请日：2006-09-12

申请人： John L. Melanson

发明人： John L. Melanson

IPC分类号： H03M1/12

CPC分类号： H03M3/412 ,  H03M3/424 ,  H03M3/452 ,  H03M3/454

摘要： An analog-to-digital converter (ADC) having a reduced number of quantizer output levels provides for reduced complexity and power consumption along with improved linearity. The analog-to-digital converter includes a loop filter, a quantizer for quantizing the output of the loop filter and a digital integrator for integrating the output of the quantizer. A difference circuit is included in the converter that produces a signal proportional to the difference between the present value and a previous value of the digital integrator output and provides feedback to the loop filter. The number of levels of the quantizer output is thereby reduced with respect to the modulator output, since the quantizer is operating on a feedback signal that represents changes in the output of the converter modulator rather than the modulator output itself.

摘要翻译： 具有减少的量化器输出电平数量的模数转换器（ADC）提供降低的复杂性和功耗以及改进的线性度。 模数转换器包括环路滤波器，用于量化环路滤波器的输出的量化器和用于对量化器的输出进行积分的数字积分器。 差分电路包括在转换器中，产生与当前值和数字积分器输出的先前值之间的差成比例的信号，并向环路滤波器提供反馈。 量化器输出的电平数量因此相对于调制器输出而减少，因为量化器在表示转换器调制器的输出的变化而不是调制器输出本身的反馈信号上操作。