公开(公告)号：US20060238232A1

公开(公告)日：2006-10-26

申请号：US11400018

申请日：2006-04-07

申请人： Jerome Bourgoin ,  Gilles Troussel

发明人： Jerome Bourgoin ,  Gilles Troussel

IPC分类号： H03L5/00

CPC分类号： H03K5/003 ,  H03K5/08 ,  H03K17/08122 ,  H03K17/6874 ,  H03K19/018571

摘要： A voltage level shifting device includes an activation or deactivation control input, first and second output nodes, a capacitor coupled between the output nodes, a high-voltage transistor for charging the capacitor, a high-voltage transistor for discharging the capacitor, a comparator which generates a charge blocking signal and a discharge signal, and a control device which is operative to cause the charging transistor to be blocked when a charge blocking signal is generated and to turn on the discharging transistor upon receipt of a deactivation control signal and when a discharge signal is generated.

公开(公告)号：US20060232297A1

公开(公告)日：2006-10-19

申请号：US11390371

申请日：2006-03-28

申请人： Takashi Tanimoto

发明人： Takashi Tanimoto

IPC分类号： H03K19/0175

CPC分类号： H03K19/018571

摘要： A driver circuit is improved in drive capability corresponding to a resolution increase for a CCD sensor while suppressing chip size of a driver circuit. A preceding-stage circuit, operating on VDD2 (>VDD) and VLOW2 (

摘要翻译： 驱动电路的驱动能力相应于CCD传感器的分辨率增加，同时抑制驱动电路的芯片尺寸。 在V DD2（> V DD）上操作的前级电路和V SUB2低电平（）被提供在在V DD和V LOW上工作的输出级电路之前的阶段中。 输出级具有当从前级电路提供栅极电压V SUB2 LOW时导通的晶体管QPd，从而在输出端Vout上输出电压V DD， / SUB>和根据电压Vgs（= V DD-LOW SUB2）的电流。 此外，晶体管QNd在被提供来自前级电路的栅极电压V DD2 时导通，从而在输出端子Vout上输出电压V LOW 以及根据电压Vgs（= VAT2-2 -V LOW）的电流。 因为这些Vgs大于V DD，所以可以提高输出级电路的驱动能力，并且相应地抑制晶体管的尺寸。

公开(公告)号：US07123237B2

公开(公告)日：2006-10-17

申请号：US10725593

申请日：2003-12-03

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Toshio Miyazawa

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Toshio Miyazawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G2310/0289 ,  H03K19/018571

摘要： The present invention provides a display device which is capable of fetching input signals of a small amplitude into the inside thereof. A level converting circuit includes a first-conductive-type first transistor having a gate electrode to which input signals are applied through a first capacitive element, a second-conductive-type second transistor having a gate electrode to which input signals are applied through a second capacitive element, a first bias circuit which applies a first bias voltage to the gate electrode of the first transistor and a second bias circuit which applies a second bias voltage to the gate electrode of the second transistor. Here, the first bias voltage is a voltage which turns off the first transistor when a voltage applied to the gate electrode of the first transistor assumes a maximum value and the second bias voltage is a voltage which turns off the second transistor when a voltage applied to the gate electrode of the second transistor assumes a minimum value.

公开(公告)号：US20050073349A1

公开(公告)日：2005-04-07

申请号：US10952149

申请日：2004-09-27

申请人： Ying-Hsin Li

发明人： Ying-Hsin Li

IPC分类号： G09G3/36 ,  H03B1/00 ,  H03K3/356 ,  H03K17/687 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185

CPC分类号： H03K19/018571 ,  G09G3/3677 ,  G09G2310/0289 ,  H03K3/356113 ,  H03K19/0013 ,  H03K19/01707

摘要： A voltage level transferring circuit is provided for transferring an input signal oscillating between a high original voltage level and a low original voltage level in a signal input terminal to a target signal oscillating between a high target voltage level and a low target voltage level in a signal output terminal. The circuit includes a voltage pull-up set including a plurality of transistor switches to pull up the voltage from the high original voltage level to the high target voltage level, and a voltage pull-down set including a plurality of transistor switches to pull down the voltage from the low original voltage level to the low target voltage level.

摘要翻译： 提供电压电平传送电路，用于将在信号输入端子中的高原始电压电平和低原始电压电平之间振荡的输入信号传送到在信号中的高目标电压电平和低目标电压电平之间振荡的目标信号 输出端子。 电路包括电压上拉组，其包括多个晶体管开关，以将电压从高原始电压电平上拉到高目标电压电平;以及电压下拉组，其包括多个晶体管开关以将下拉 电压从低原始电压电平到低目标电压电平。

公开(公告)号：US20040160258A1

公开(公告)日：2004-08-19

申请号：US10355286

申请日：2003-01-31

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Youichi Tobita

IPC分类号： H03L005/00

CPC分类号： G09G3/3688 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018571

摘要： A drive circuit includes: a first level shift circuit outputting a potential higher than an input potential by a prescribed voltage; a pull-up circuit outputting a potential lower than an output potential of the first level shift circuit by the prescribed voltage to an output node; a second level shift circuit outputting a potential lower than the input potential by the prescribed voltage; a pull-down circuit outputting a potential higher than an output potential of the second level shift circuit by the prescribed voltage to output node; and a capacitor connected between output nodes of the first and second level shift circuits. Accordingly, a through-current is reduced.

摘要翻译： 驱动电路包括：第一电平移位电路，输出比输入电位高于规定电压的电位; 上拉电路，将低于所述第一电平移位电路的输出电位的电位通过所述规定电压输出到输出节点; 第二电平移位电路，将低于输入电位的电位输出规定电压; 下降电路，通过规定的电压向输出节点输出高于第二电平移位电路的输出电位的电位; 以及连接在第一和第二电平移位电路的输出节点之间的电容器。 因此，减小了通流。

公开(公告)号：US06433606B1

公开(公告)日：2002-08-13

申请号：US09633858

申请日：2000-08-07

申请人： Kenji Arai

发明人： Kenji Arai

IPC分类号： H03K300

CPC分类号： G06F1/10 ,  H03K5/151 ,  H03K19/018571

摘要： Disclosed herein are a clock driver circuit and a method of routing clock interconnect lines, which control the lengths of adjacent interconnect lines and ununiformity of conductive line capacitance due to the intersection of interlayer interconnect lines, thereby reducing clock skews. The clock driver circuit comprises an input terminal to which a single-phase clock signal is inputted, an initial-stage clock driver circuit which is connected to the input terminal and which converts the single-phase clock signal to positive-phase and anti-phase clock signals, an intermediate clock driver circuits which respectively relay the positive-phase and anti-phase clock signals outputted from the initial-stage clock driver circuit, a final-stage clock driver circuits which respectively convert the positive-phase and anti-phase clock signals relayed by the intermediate clock driver circuits to single-phase clock signals, and a pair of interconnect lines which respectively connect between the initial-stage clock driver circuit and the final-stage clock driver circuits through the intermediate clock driver circuits and transmit positive-phase and anti-phase clock signals. The interconnect lines are placed as adjacent to each other.

摘要翻译： 这里公开了一种时钟驱动器电路和路由时钟互连线路的方法，其控制相邻互连线的长度以及由于层间互连线的交叉而导致的线路电容的不均匀性，从而减少时钟偏差。 时钟驱动器电路包括输入单相时钟信号的输入端子，连接到输入端子并将单相时钟信号转换为正相和反相的初级时钟驱动电路 时钟信号，分别中继从初级时钟驱动电路输出的正相和反相时钟信号的中间时钟驱动器电路，分别转换正相和反相时钟的最后一级时钟驱动电路 由中间时钟驱动器电路中继到单相时钟信号的信号，以及一对互连线，其通过中间时钟驱动器电路分别连接在初级时钟驱动电路和最后级时钟驱动器电路之间， 相位和反相时钟信号。 互连线彼此相邻放置。

公开(公告)号：US5761244A

公开(公告)日：1998-06-02

申请号：US352863

申请日：1994-12-02

申请人： Mats Olof Joakim Hedberg

发明人： Mats Olof Joakim Hedberg

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H04L25/02 ,  H04B3/02 ,  H04L25/00

CPC分类号： H03K19/018571

摘要： A signalling system adapted for digital signals includes a signal transmitter, a signal receiver and a connection which connects the transmitter to the receiver. The transmitter includes an output buffer which has at least one transistor connected to the lowest level of a signal supply voltage, such as to "0" potential or earth potential. Driving or steering of the transistor in response to a received control signal causes the transistor to switch from a state of high impedance to a state of low impedance which exhibits resistive or at least predominantly resistive properties, such as to form an information-carrying output signal. A first of two series-connected transistors is connected to the lowest level of the signal supply voltage, for instance "0" or earth potential, and the other transistor is connected to the signal supply voltage. A connection conductor on which the information-carrying signal is transmitted is connected between the transistors. The transistors are brought to different states simultaneously, and in a state of low-impedance, the impedance value corresponds to the impedance value (the resistance value) of the connection.

摘要翻译： 适用于数字信号的信令系统包括信号发射机，信号接收机和将发射机连接到接收机的连接。 发射机包括输出缓冲器，其具有连接到信号电源电压的最低电平的至少一个晶体管，例如“0”电位或地电位。 晶体管响应于接收的控制信号而驱动或转向导致晶体管从高阻抗状态切换到呈现电阻性或至少主要是电阻特性的低阻抗状态，例如形成信息传送输出信号 。 两个串联晶体管中的第一个连接到信号电源电压的最低电平，例如“0”或地电位，另一个晶体管连接到信号电源电压。 在其上传输信息载体信号的连接导体连接在晶体管之间。 晶体管同时处于不同状态，并且在低阻抗状态下，阻抗值对应于连接的阻抗值（电阻值）。

公开(公告)号：US5729154A

公开(公告)日：1998-03-17

申请号：US715358

申请日：1996-09-10

申请人： Masao Taguchi ,  Tsuyoshi Higuchi

发明人： Masao Taguchi ,  Tsuyoshi Higuchi

IPC分类号： G06F13/40 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H03K17/16 ,  H03K19/0175

CPC分类号： H04L25/028 ,  H03K19/00384 ,  H03K19/018571 ,  H04L25/0278 ,  H04L25/0298 ,  H04L25/0266 ,  H04L25/0292

摘要： An electronic system includes a plurality of electronic circuits each having a signal input and output function, a bus to which the plurality of electronic circuits are connected, first termination resistors connected to ends of the bus, and a termination voltage circuit having a first part generating a first voltage and a second part generating a second voltage. The sum of the first voltage and the second voltage is supplied, as a power supply voltage, to output circuits of the plurality of electronic circuits connected to the bus. The second voltage is supplied to the first termination resistors as a termination voltage.

公开(公告)号：US5514983A

公开(公告)日：1996-05-07

申请号：US360325

申请日：1994-12-21

申请人： Ryozo Yoshino

发明人： Ryozo Yoshino

IPC分类号： G06F3/00 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H04B1/04 ,  H04B1/40 ,  H04L5/14 ,  H04L25/02

CPC分类号： H04L25/028 ,  H03K19/0005 ,  H03K19/018571 ,  H04L25/0278 ,  H04L25/0292 ,  H04L5/1423 ,  H04L25/0272

摘要： The data input/output circuit for full duplex communication includes a data accepting and sending circuit which has an input/output terminal connected to a processor provided within a digital apparatus, and which receives data from the processor, transmits the data and receives outside data through the input/output terminal, a reference circuit which divides a voltage level of the data transmitted from the data accepting and sending circuit and produces a divided voltage level, a differential receiving circuit which has one input terminal connected to the input/output terminal and another input terminal connected to the reference circuit, and which is not operated by a zero voltage difference between the input terminals when the data is transmitted from the input/output terminal but operated by a voltage difference between the input terminals when the data is received through the input/output terminal, the data being supplied to the processor of the digital apparatus, a reference circuit for generating an output impedance value of the data accepting and sending circuit, and a voltage regulation circuit for adjusting a power supply voltage to be applied to the data accepting and sending circuit so that the output impedance value is changed in accordance with the value of the output impedance. This data input/output circuit can be incorporated in an LSI of CMOS transistor structure and has a simple circuit arrangement capable of impedance matching with the transmission path.

摘要翻译： 用于全双工通信的数据输入/输出电路包括数据接收和发送电路，其具有连接到设置在数字设备内的处理器的输入/输出端子，并且从处理器接收数据，发送数据并通过 输入/输出端子，分配从数据接收和发送电路发送的数据的电压电平并产生分压电压电平的参考电路;差分接收电路，其具有连接到输入/输出端子的一个输入端子和另一个 输入端子连接到参考电路，并且当数据从输入/输出端子发送时不在输入端子之间的零电压差下操作，而是当通过输入端子接收数据时通过输入端子之间的电压差来操作 输入/输出端子，提供给数字设备的处理器的数据，参考电路 用于产生数据接收和发送电路的输出阻抗值的电压调节电路，以及用于调整要施加到数据接收和发送电路的电源电压的电压调节电路，使得输出阻抗值根据 输出阻抗。 该数据输入/输出电路可以结合在CMOS晶体管结构的LSI中，并且具有能够与传输路径进行阻抗匹配的简单的电路布置。

公开(公告)号：US5438281A

公开(公告)日：1995-08-01

申请号：US136946

申请日：1993-10-18

申请人： Toshiro Takahashi ,  Kazuo Koide

发明人： Toshiro Takahashi ,  Kazuo Koide

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G11C11/401 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02 ,  H03K19/094 ,  H03K17/16

CPC分类号： H04L25/028 ,  H01L27/11898 ,  H03K19/018571 ,  H03K19/018592 ,  H04L25/0292 ,  H04L25/0298

摘要： Data to be processed are transferred by connecting a one-way element having a reduced parasitic capacitance such as the Schottky diode between an output MOSFET having an open drain structure and an output terminal to be connected with a bus line terminated by an impedance element.

摘要翻译： 要处理的数据是通过将具有减小的寄生电容的单向元件（例如肖特基二极管）连接到具有开漏结构的输出MOSFET和与由阻抗元件端接的总线连接的输出端子之间传送的。