公开(公告)号：US06873828B2

公开(公告)日：2005-03-29

申请号：US09855030

申请日：2001-05-15

申请人： Tetsuro Asano ,  Takayoshi Higashino ,  Koichi Hirata

发明人： Tetsuro Asano ,  Takayoshi Higashino ,  Koichi Hirata

IPC分类号： H01L21/338 ,  H01L21/8232 ,  H01L27/06 ,  H01L29/812 ,  H01P1/15 ,  H03K17/00 ,  H03K17/041 ,  H03K17/693 ,  H04B1/44

CPC分类号： H01L29/812 ,  H01L27/0605 ,  H03K17/04106 ,  H03K17/693

摘要： A compound semiconductor switching device is based on a designing guideline that isolation should be assured by reducing the gate width of switching FET, thereby reducing the capacitance of the FET. Proper isolation between the two signal passes IS obtained with a FET gate width of about 700 μm or smaller at a signal frequency of about 2.4 GHz or higher, without employing a shunt FET.

摘要翻译： 复合半导体开关器件基于设计指南，通过减小开关FET的栅极宽度来确保隔离，从而降低FET的电容。 在大约2.4GHz或更高的信号频率下，以大约700μm或更小的FET栅极宽度获得两个信号通路IS之间的适当隔离，而不使用分流FET。

公开(公告)号：US06864539B2

公开(公告)日：2005-03-08

申请号：US10618710

申请日：2003-07-15

申请人： Koichiro Ishibashi ,  Takahiro Yamashita

发明人： Koichiro Ishibashi ,  Takahiro Yamashita

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L27/092 ,  H03K17/041 ,  H03K19/003 ,  H03K19/017 ,  H01L23/62

CPC分类号： H01L27/0928 ,  H01L27/0218 ,  H01L27/0727 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/04106 ,  H03K19/00384 ,  H03K19/01707 ,  Y10S257/901 ,  H01L2924/00

摘要： A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.

摘要翻译： 半导体集成电路器件具有MISFET和主体偏置电路。 MISFET具有第一导电类型的源电极和漏电极和栅电极，并且MISFET形成在第二导电类型的阱中。 主体偏置电路通过将正向的规定电流传递到由阱和MISFET的源电极形成的二极管中，在阱中产生电压。

公开(公告)号：US20050035663A1

公开(公告)日：2005-02-17

申请号：US10633606

申请日：2003-07-31

申请人： Steven Moore ,  John Santhoff

发明人： Steven Moore ,  John Santhoff

IPC分类号： H03K17/041 ,  H03K17/693 ,  H03K3/00

CPC分类号： H03K17/04106 ,  H03K17/693

摘要： A system, method and apparatus for an electromagnetic pulse generator is provided. In one embodiment of the present invention, a computer software interface provides control signals to an array of electromagnetic pulse generation gates. Electromagnetic pulses generated by the array of electromagnetic pulse generation gates may be aggregated to form a desired waveform. One feature of the invention is that the electromagnetic waveforms generated are compatible with a number of different communications methods and technologies. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

摘要翻译： 提供了一种用于电磁脉冲发生器的系统，方法和装置。 在本发明的一个实施例中，计算机软件接口向电磁脉冲产生门阵列提供控制信号。 由电磁脉冲产生门阵列产生的电磁脉冲可以被聚集以形成期望的波形。 本发明的一个特征是产生的电磁波形与多种不同的通信方法和技术兼容。 本摘要仅用于遵守允许读者快速确定本文所包含的披露的主题的抽象要求规则。 本摘要以明确的理解提交，不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US06836234B1

公开(公告)日：2004-12-28

申请号：US10665618

申请日：2003-09-22

申请人： Hongwei Wang

发明人： Hongwei Wang

IPC分类号： H03M166

CPC分类号： H03K17/04106 ,  H03K17/04123

摘要： A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates drive signals based on received respective digital input signals. The drive signals are received at respective switches in the analog section. The driver portion includes logic gates that are used to generate the drive signals, such that a rise and fall time of complementary pairs of drive signals are substantially equal. The driver portion can optionally include an acceleration system to accelerate the rise and fall times of the drive signals. The switches generate respective analog signals from the drive signals.

摘要翻译： 系统（例如，数模转换器（DAC））包括数字部分和模拟部分。 数字部分具有基于接收的相应数字输入信号产生驱动信号的驱动器部分。 在模拟部分的相应开关处接收驱动信号。 驱动器部分包括用于产生驱动信号的逻辑门，使得互补驱动信号对的上升和下降时间基本相等。 驱动器部分可以可选地包括加速系统以加速驱动信号的上升和下降时间。 开关从驱动信号产生相应的模拟信号。

公开(公告)号：US20040257255A1

公开(公告)日：2004-12-23

申请号：US10893999

申请日：2004-07-20

申请人： Broadcom Corporation

发明人： Jan Mulder

IPC分类号： H03M001/12

CPC分类号： H03M1/0863 ,  H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/36 ,  H03M1/365

摘要： An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase null2 and substantially rejecting the signal corresponding to the output signal during the clock phase null1.

摘要翻译： 输入级包括在每个阵列中串联布置的多个自动调零放大器阵列，其中每个自动调零放大器接收前一自动调零放大器的输出，其中每个阵列放大器中的第一自动调零放大器接收输入信号和对应的参考电压 其输入，并且其中至少一个自动调零放大器包括接收对应于输出信号的信号的电路，该电路在时钟相位phi2期间基本上将对应于输出信号的信号和参考电压传送到放大器，并且基本上 在时钟相位phi1期间拒绝对应于输出信号的信号。

公开(公告)号：US06833801B1

公开(公告)日：2004-12-21

申请号：US10724645

申请日：2003-12-01

申请人： Geir Sigurd Ostrem ,  Paul W. Kalthoff

发明人： Geir Sigurd Ostrem ,  Paul W. Kalthoff

IPC分类号： H03M166

CPC分类号： H03M1/0678 ,  H03K17/04106 ,  H03M1/742

摘要： Low distortion current switches for high speed current steering digital-to-analog converters. The current switches use a compensation method for improving the spurious peformance of a CMOS current steering DAC for high output frequencies caused by the capacitance of the common node of the switch transistors. For this purpose, a replica switch is provided, with the voltage change on the common node of the replica switch being used to provide a corresponding charge to the common node of the main switch in an amount equal to the charge needed to change the voltage on the common node of the main switch by the same amount as the voltage change on the common node of the replica switch. Multiple embodiments are disclosed.

摘要翻译： 低失真电流开关用于高速电流转向数模转换器。 电流开关使用补偿方法来改善由CMOS开关晶体管的公共节点的电容引起的高输出频率的CMOS电流转向DAC的杂散性能。 为此，提供了复制开关，其中副本开关的公共节点上的电压变化用于向主开关的公共节点提供相当于电荷变化所需的电荷量的相应电荷 主开关的公共节点与复制开关的公共节点上的电压变化相同。 公开了多个实施例。

公开(公告)号：US06819143B1

公开(公告)日：2004-11-16

申请号：US10388138

申请日：2003-03-13

申请人： Tae-Song Chung

发明人： Tae-Song Chung

IPC分类号： G01R1900

CPC分类号： H03K17/04106 ,  H03K19/018528

摘要： An input buffer circuit includes a first differential circuit, a second differential circuit, a pull-up circuit, and a pull-down circuit. An input voltage and a reference voltage are provided to the first and second differential circuits. The first differential circuit detects rising edges of the input voltage and causes the pull-up circuit to quickly drive an output voltage to logic high. The second differential circuit detects falling edges of the input voltage and causes the pull-down circuit to quickly drive the output voltage to logic low.

摘要翻译： 输入缓冲电路包括第一差分电路，第二差分电路，上拉电路和下拉电路。 输入电压和参考电压被提供给第一和第二差分电路。 第一个差分电路检测输入电压的上升沿，并使上拉电路将输出电压快速驱动到逻辑高电平。 第二个差分电路检测输入电压的下降沿，并使下拉电路快速驱动输出电压为逻辑低电平。

公开(公告)号：US06812735B1

公开(公告)日：2004-11-02

申请号：US10397496

申请日：2003-03-26

申请人： Hiep The Pham

发明人： Hiep The Pham

IPC分类号： H03K1716

CPC分类号： H04L25/0278 ,  H03K17/04106 ,  H03K17/167 ,  H04L25/0276 ,  H04L25/028

摘要： A termination resistor circuit includes a first and second passive resistive elements coupled in series between a common mode voltage and a signal node, and a plurality of active resistive elements coupled in parallel with the first passive resistive element. The active resistive elements may be selectively enabled by corresponding control signals to provide various numbers of parallel resistances across the first passive resistive element, thereby tuning the termination resistor circuit to a desired resistance value.

摘要翻译： 终端电阻电路包括串联耦合在共模电压和信号节点之间的第一和第二无源电阻元件以及与第一被动电阻元件并联耦合的多个有源电阻元件。 有源电阻元件可以通过对应的控制信号选择性地使能，以在第一无源电阻元件上提供不同数量的并联电阻，从而将终端电阻电路调谐到期望的电阻值。

公开(公告)号：US06697005B2

公开(公告)日：2004-02-24

申请号：US10158774

申请日：2002-05-31

申请人： Jan Mulder

发明人： Jan Mulder

IPC分类号： H03M112

CPC分类号： H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/365 ,  H04L25/026 ,  H04L25/0276

摘要： An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

摘要翻译： N位模数转换器包括连接到一端的输入电压并在另一端接地的参考梯形图，其差分放大器的阵列与差分输入端连接到来自参考梯形图的抽头，其中每个放大器具有 连接到与相邻放大器相同的抽头的第一差分输入和从相邻放大器偏移一抽头的第二差分输入，以及将阵列的输出转换为N位输出的编码器。

公开(公告)号：US20030201920A1

公开(公告)日：2003-10-30

申请号：US10431103

申请日：2003-05-06

申请人： Broadcom Corporation

发明人： Bo Zhang

IPC分类号： H03M009/00

CPC分类号： H03M9/00 ,  H03K3/356043 ,  H03K3/356139 ,  H03K3/3562 ,  H03K17/04106 ,  H03K17/693 ,  H03K2005/00208 ,  H04J3/047

摘要： In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

摘要翻译： 根据本发明，数据处理电路包括用于处理第一数据的第一数据路径。 第一数据路径包括第一数据存储电路。 提供第二数据路径用于处理第二数据。 第二数据路径包括第二数据存储电路。 具有耦合到第一数据路径的第一输入和耦合到第二数据路径的第二输入的多路复用器接收存储的值。 复用器包括耦合到时钟信号的选择输入。 延迟电路被配置为延迟第二数据存储电路中的第二数据的存储，其中第一数据存储电路响应于接收到第一定时信号而存储第一数据，并且第二数据存储电路存储第二数据作为响应 以接收第二定时信号。