公开(公告)号：US09015504B2

公开(公告)日：2015-04-21

申请号：US12986127

申请日：2011-01-06

Applicant: Thang Tran

Inventor： Thang Tran

IPC: G06F1/32 ,  G06F9/46 ,  G06F9/38 ,  G06F9/32 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885

Abstract: A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power management configuration; and (3) a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads, wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.

Abstract translation: 一种用于处理线程中的指令的多线程微处理器，包括在一个实施例中，（1）用于指令的至少一个处理器流水线; （2）用于线程电源管理配置的存储器; 以及（3）功率控制电路，其耦合到所述至少一个处理器流水线并响应所述存储器进行线程电源管理配置以根据所述线程来控制所述至少一个处理器管线的不同部分使用的功率，其中所述功率控制电路 可操作以根据线程在至少一个处理器管线的不同部分中建立不同的电源电压。

公开(公告)号：US20140164739A1

公开(公告)日：2014-06-12

申请号：US13710494

申请日：2012-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind ,  Eric M. Schwarz

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/324 ,  G06F9/342

Abstract: An modify next sequential instruction (MNSI) instruction, when executed, modifies a field of the fetched copy of the next sequential instruction (NSI) to enable a program to dynamically provide parameters to the NSI being executed. Thus the MNSI instruction is a non-disruptive prefix instruction to the NSI. The NSI may be modified to effectively extend the length of the NSI field, thus providing more registers or more range (in the case of a length field) than otherwise available to the NSI instruction according to the instruction set architecture (ISA)

公开(公告)号：US08275978B1

公开(公告)日：2012-09-25

申请号：US12504080

申请日：2009-07-16

Applicant: Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

Inventor： Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

IPC: G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806

Abstract: In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the microprocessor. The branch circuit is coupled to the pipeline circuit and operates to store branch information. The control circuit is coupled to the pipeline circuit and the branch circuit. The control circuit stores a first branch information from the pipeline circuit to the branch circuit when a first condition is met. The control circuit retrieves a second branch information from the branch stack circuit to the pipeline circuit when a second condition is met. In this manner, the need for dedicated pipeline flush circuitry is avoided.

Abstract translation: 在一个实施例中，本发明包括具有流水线电路，分支电路和控制电路的微处理器。 管道电路管道指令为微处理器。 分支电路耦合到流水线电路并操作以存储分支信息。 控制电路耦合到流水线电路和分支电路。 当满足第一条件时，控制电路将来自流水线电路的第一分支信息存储到分支电路。 当满足第二条件时，控制电路从分支堆栈电路检索第二分支信息到流水线电路。 以这种方式，避免了专用管道冲洗电路的需要。

公开(公告)号：US20110161634A1

公开(公告)日：2011-06-30

申请号：US12926350

申请日：2010-11-12

Applicant: Hiroaki Sakaguchi

Inventor： Hiroaki Sakaguchi

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30134 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3881

Abstract: A processor includes a buffer that separates a sequence of instructions having no operand into segments and stores the segments, a data holder that holds data to be processed, a decoder that references the data and sequentially decodes at least one of the instructions from the top of the sequence, an instruction execution unit that executes the instruction, and an instruction sequence control unit that controls updating of the instruction sequence in accordance with the decoding result. When the decoded top instruction is a branch instruction and if a branch is taken, the instruction sequence control unit updates the sequence so that the top instruction of one of the segments is located at the top of the sequence. If a branch is not taken, the instruction sequence control unit updates the sequence so that an instruction immediately next to the branch instruction is located at the top of the sequence.

Abstract translation: 处理器包括一个缓冲器，该缓冲器将没有操作数的指令序列分离成段并存储段，保存要处理数据的数据保持器，引用该数据的解码器，并从至少一个指令从 所述序列，执行所述指令的指令执行单元，以及根据所述解码结果控制所述指令序列的更新的指令序列控制单元。 当解码的顶部指令是分支指令并且如果采用分支时，指令序列控制单元更新该序列，使得其中一个段的顶部指令位于序列的顶部。 如果不采取分支，则指令序列控制单元更新序列，使得紧邻分支指令的指令位于序列的顶部。

公开(公告)号：US07877578B2

公开(公告)日：2011-01-25

申请号：US12071586

申请日：2008-02-22

Applicant: Yasuhiro Yamazaki

Inventor： Yasuhiro Yamazaki

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC classification number: G06F9/30058 ,  G06F9/3017 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/3844

Abstract: The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction and instruction type information indicating a type of the conditional branch instruction when the input instruction is a conditional branch instruction, and writing the input instruction, from which the operation code is deleted, the conditional branch instruction information and the instruction type information to the instruction cache memory, and a history information writing unit writing history information indicating whether or not the conditional branch instruction was branched, as a result of executing the conditional branch instruction stored in the instruction cache memory, to an area in the instruction cache memory, where the operation code of the conditional branch instruction is deleted.

Abstract translation: 本发明提供了一种信息处理装置，其具有对输入指令中的操作码进行解码的预解码器，生成指示输入指令是条件转移指令的条件转移指令信息和指示条件转移指令的类型的指令类型信息， 指令是条件分支指令，并且将指定了运算代码的输入指令从条形分支指令信息和指令类型信息写入到指令高速缓冲存储器，以及历史信息写入部，写入表示是否进行历史信息 作为执行存储在指令高速缓存存储器中的条件转移指令的结果，条件转移指令被分支到指令高速缓存存储器中的区域，在该区域中，条件转移指令的操作代码被删除。

公开(公告)号：US07823142B2

公开(公告)日：2010-10-26

申请号：US11245357

申请日：2005-10-07

Applicant: Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

Inventor： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC: G06F9/45

CPC classification number: G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract translation: 当指令解码器409a至409c解码分支指令时，分支指令中包括的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US20090182984A1

公开(公告)日：2009-07-16

申请号：US11972714

申请日：2008-01-11

Applicant: Dan F. Greiner ,  Timothy J. Slegel ,  Charles W. Gainey

Inventor： Dan F. Greiner ,  Timothy J. Slegel ,  Charles W. Gainey

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30167 ,  G06F9/324 ,  G06F9/342 ,  G06F9/355

Abstract: A method, system and program product for an execute relative instruction, which when executed fetches and executes a target instruction at a relative address and then returns processing to the next instruction following the execute relative instruction. The relative address is formed by adding the value of the program counter to a sign extended immediate field. The fetched target instruction is optionally modified before execution by OR'ing bits into predetermined bits of the target instruction.

Abstract translation: 一种用于执行相关指令的方法，系统和程序产品，其在执行时在相对地址处获取并执行目标指令，然后在执行相关指令之后向下一个指令返回处理。 通过将程序计数器的值添加到符号扩展的立即数字段来形成相对地址。 所获取的目标指令在执行之前可选地被修改以将位对准目标指令的预定位。

公开(公告)号：US20080320247A1

公开(公告)日：2008-12-25

申请号：US11983754

申请日：2007-11-08

Applicant: Alistair G. Morfey ,  Karl Leighton Swepson ,  Neil Edward Johnson ,  Martin David Cooper ,  Alan Mycroft

Inventor： Alistair G. Morfey ,  Karl Leighton Swepson ,  Neil Edward Johnson ,  Martin David Cooper ,  Alan Mycroft

IPC: G06F12/00

CPC classification number: G06F1/24 ,  G06F8/4434 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/324 ,  G06F11/10

Abstract: A data processing apparatus comprises a processor constructed to operate under control of a sequence of program instructions selected from a predetermined instruction set; master circuitry to request access to storage locations of the processor; an interface circuit to provide an interface for an external apparatus to signal a request for access to the storage locations and an interface for the master circuitry to signal a request for access to the storage locations; and control to provide access between the storage locations and the interface circuit in response to the request only at predetermined points in execution of the stored program, the control being operable to fix periods of time for providing such access relative to the sequence of program instructions such that execution timing of the stored instructions is independent of whether a request is supplied to the interface.

Abstract translation: 一种数据处理装置，包括：处理器，被构造成在从预定指令集中选择的程序指令序列的控制下进行操作; 主电路请求访问处理器的存储位置; 接口电路，用于提供用于外部设备的接口，用于向接入存储位置发出信号请求;以及接口，用于主电路向接收存储位置的信号通知信号; 以及控制以仅在存储的程序的执行中的预定点响应于该请求而在存储位置和接口电路之间提供接入，该控制可操作以固定相对于程序指令序列提供这种访问的时间段， 所存储的指令的执行定时与是否向该接口提供请求无关。

公开(公告)号：US07409535B2

公开(公告)日：2008-08-05

申请号：US11110240

申请日：2005-04-20

Applicant: Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

Inventor： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/30061 ,  G06F9/324

Abstract: An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern in a plurality of target addresses for a multi-target branch. The information processing system further includes logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified.

Abstract translation: 公开了一种用于分支目标预测的信息处理系统。 信息处理系统包括用于存储条目的存储器，其中每个条目包括表示多目标分支的目标地址的历史的多个目标地址和用于读取存储器的逻辑，以及识别多个目标地址中的重复模式， 多目标分支。 信息处理系统还包括用于基于所识别的重复模式预测多目标分支的下一目标地址的逻辑。

公开(公告)号：US07272704B1

公开(公告)日：2007-09-18

申请号：US10844941

申请日：2004-05-13

Applicant: Hung Nguyen ,  Shannon Wichman

Inventor： Hung Nguyen ,  Shannon Wichman

IPC: G06F9/44

CPC classification number: G06F9/325 ,  G06F9/30058 ,  G06F9/324 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3875 ,  G06F9/3885

Abstract: A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may provide zero-overhead looping for branch instructions, in addition to single loop constructs and multiple loop constructs (which may or may not be nested). Zero-overhead looping may also be provided in special cases, e.g., when servicing an interrupt or executing a branch-out-of-loop instruction. In addition to reducing the number of instructions required to execute a program, as well as the overall time and power consumed during program execution, the hardware looping mechanism described herein may be integrated within any processor architecture without modifying existing program code.

Abstract translation: 本文描述了用于处理在标量或超标量处理器中执行程序指令时可能出现的任何数量和/或类型的不连续指令的硬件循环机制和方法。 例如，除了单个循环结构和多个循环结构（其可以嵌套或可以不嵌套）之外，硬件循环机制可以为分支指令提供零开销循环。 在特殊情况下也可以提供零开销循环，例如当服务于中断或执行分支回路指令时。 除了减少执行程序所需的指令数量以及在程序执行期间消耗的总体时间和功耗之外，本文描述的硬件循环机制可以集成在任何处理器架构中而不修改现有的程序代码。