公开(公告)号：US20080313433A1

公开(公告)日：2008-12-18

申请号：US12196102

申请日：2008-08-21

Applicant: Hung Nguyen ,  Shannon Wichman

Inventor： Hung Nguyen ,  Shannon Wichman

IPC: G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30072

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

Abstract translation: 公开了一种处理器，其包括允许处理器同时执行多个条件执行指令组的指令的若干特征。 每个条件执行指令组包括条件执行指令和由条件执行指令指定的代码块。 在一个实施例中，处理器包括多个寄存器，用于存储与多个执行流水线级中的每一个中的多个指令有关的标记数据。 在另一个实施例中，处理器包括写使能逻辑和执行单元。 写使能逻辑根据接收的属性产生写使能信号，执行单元根据写使能信号保存条件执行指令组的指令结果。

公开(公告)号：US20060101251A1

公开(公告)日：2006-05-11

申请号：US11273679

申请日：2005-11-14

Applicant: Hung Nguyen ,  Shannon Wichman

Inventor： Hung Nguyen ,  Shannon Wichman

IPC: G06F9/44

CPC classification number: G06F9/3853 ,  G06F9/30072

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

Abstract translation: 公开了一种处理器，其包括允许处理器同时执行多个条件执行指令组的指令的若干特征。 每个条件执行指令组包括条件执行指令和由条件执行指令指定的代码块。 在一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个状态机。 在另一个实施例中，处理器包括多个寄存器，用于存储与多个执行流水线级中的每一个中的多个指令有关的标记数据。 在另一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个属性队列。 在另一个实施例中，处理器包括写使能逻辑和执行单元。 写使能逻辑根据接收的属性产生写使能信号，执行单元根据写使能信号保存条件执行指令组的指令结果。

公开(公告)号：US07020765B2

公开(公告)日：2006-03-28

申请号：US10256410

申请日：2002-09-27

Applicant: Hung Nguyen ,  Shannon Wichman

Inventor： Hung Nguyen ,  Shannon Wichman

IPC: G06F9/40

CPC classification number: G06F9/3853 ,  G06F9/30072

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

Abstract translation: 公开了一种处理器，其包括允许处理器同时执行多个条件执行指令组的指令的若干特征。 每个条件执行指令组包括条件执行指令和由条件执行指令指定的代码块。 在一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个状态机。 在另一个实施例中，处理器包括多个寄存器，用于存储与多个执行流水线级中的每一个中的多个指令有关的标记数据。 在另一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个属性队列。 在另一个实施例中，处理器包括写使能逻辑和执行单元。 写使能逻辑根据接收的属性产生写使能信号，执行单元根据写使能信号保存条件执行指令组的指令结果。

公开(公告)号：US07418578B2

公开(公告)日：2008-08-26

申请号：US11273679

申请日：2005-11-14

Applicant: Hung Nguyen ,  Shannon Wichman

Inventor： Hung Nguyen ,  Shannon Wichman

IPC: G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30072

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

Abstract translation: 公开了一种处理器，其包括允许处理器同时执行多个条件执行指令组的指令的若干特征。 每个条件执行指令组包括条件执行指令和由条件执行指令指定的代码块。 在一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个状态机。 在另一实施例中，处理器包括多个寄存器，用于存储与多个执行流水线级中的每一个中的多个指令有关的标记数据。 在另一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个属性队列。 在另一个实施例中，处理器包括写使能逻辑和执行单元。 写使能逻辑根据接收的属性产生写使能信号，执行单元根据写使能信号保存条件执行指令组的指令结果。

公开(公告)号：US07272704B1

公开(公告)日：2007-09-18

申请号：US10844941

申请日：2004-05-13

Applicant: Hung Nguyen ,  Shannon Wichman

Inventor： Hung Nguyen ,  Shannon Wichman

IPC: G06F9/44

CPC classification number: G06F9/325 ,  G06F9/30058 ,  G06F9/324 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3875 ,  G06F9/3885

Abstract: A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may provide zero-overhead looping for branch instructions, in addition to single loop constructs and multiple loop constructs (which may or may not be nested). Zero-overhead looping may also be provided in special cases, e.g., when servicing an interrupt or executing a branch-out-of-loop instruction. In addition to reducing the number of instructions required to execute a program, as well as the overall time and power consumed during program execution, the hardware looping mechanism described herein may be integrated within any processor architecture without modifying existing program code.

Abstract translation: 本文描述了用于处理在标量或超标量处理器中执行程序指令时可能出现的任何数量和/或类型的不连续指令的硬件循环机制和方法。 例如，除了单个循环结构和多个循环结构（其可以嵌套或可以不嵌套）之外，硬件循环机制可以为分支指令提供零开销循环。 在特殊情况下也可以提供零开销循环，例如当服务于中断或执行分支回路指令时。 除了减少执行程序所需的指令数量以及在程序执行期间消耗的总体时间和功耗之外，本文描述的硬件循环机制可以集成在任何处理器架构中而不修改现有的程序代码。